System and method for supporting alternate number format for efficient multiplication

Patent metadata

Field	Value
Publication number	US-10977002-B2
Application number	US-201916511085-A
Country	US
Kind code	B2
Filing date	Jul 15, 2019
Priority date	Jul 15, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2n, the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.

First claim

What is claimed is:

1. A device comprising:
circuitry comprising shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network, the first value having a predetermined format comprising a first bit, and two or more second bits to represent a value of zero or 2 n wherein n is an integer greater than or equal to 0, the circuitry configured to:
when the two or more second bits represent the value of 2 n , shift the second value by (n+1) bits via the shift circuitry to provide a first multiplication result,
based on a value of the first bit of the first value, selectively output zero or the second value to provide a second multiplication result, and
add the first multiplication result and the second multiplication result via the add circuitry to provide a result of the multiplication of the first value and the second value.

2. The device according to claim 1 , wherein the first bit of the first value is a least significant bit of the first value.

3. The device according to claim 1 , wherein the circuitry is configured to provide, when the two or more second bits represent the value of zero, the value of zero as the first multiplication result.

4. The device according to claim 1 , wherein the second value uses a linear number format to represent a binary number.

5. The device according to claim 1 , wherein:
the second value has the predetermined format comprising a first bit, and two or more second bits to represent a value of zero or 2 m wherein m is an integer greater than or equal to zero, the circuitry is further configured to:
when the two or more second bits of the first value represent the value of 2 n and the two or more second bits of the second value represent the value of 2 m , shift the value of 2 m+1 by (n+1) bits via the shift circuitry to provide a third multiplication result,
based on a value of the first bit of the second value, selectively output zero or the value of 2 n+1 to provide a fourth multiplication result,
based on the value of the first bit of the first value, selectively output zero or the value of 2 m+1 to provide a fifth multiplication result,
based on the value of the first bit of the first value, selectively output zero or the value of the first bit of the second value to provide a sixth multiplication result, and
add the third to sixth multiplication results via the add circuitry to provide a result of the multiplication of the first value and the second value.

6. The device according to claim 1 , wherein “1 1” as the two or more second bits of the first value represents a value of 4.

7. The device according to claim 1 , wherein the first value further comprises a third bit to indicate that the first value is signed or unsigned.

8. The device according to claim 7 , wherein the circuitry is configured to determine a sign of the result of the multiplication of the first value and the second value based on a value of the third bit of the first value.

9. The device according to claim 1 , wherein:
the circuitry is further configured to perform convolution for a first layer of the neural network using weight data and activation data representing an activation function, and
the first value represents a value of one of the weight data and the activation data for the first layer of the neural network.

10. The device according to claim 9 , wherein the second value represents a value of the other of the weight data and the activation data for the first layer of the neural network.

11. A method comprising:
performing multiplication of a first value and a second value for a neural network, the first value having a predetermined format comprising a first bit, and two or more second bits to represent a value of zero or 2 n wherein n is an integer greater than or equal to 0,
wherein performing the multiplication of the first value and the second value comprises:
when the two or more second bits represent the value of 2 n , shifting, by shift circuitry, the second value by (n+1) bits to provide a first multiplication result,
based on a value of the first bit of the first value, selectively outputting zero or the second value to provide a second multiplication result, and
adding, by add circuitry, the first multiplication result and the second multiplication result to provide a result of the multiplication of the first value and the second value.

12. The method according to claim 11 , wherein the first bit of the first value is a least significant bit of the first value.

13. The method according to claim 11 , wherein performing the multiplication of the first value and the second value comprises:
providing, when the two or more second bits represent the value of zero, the value of zero as the first multiplication result.

14. The method according to claim 11 , wherein the second value uses a linear number format to represent a binary number.

15. The method according to claim 11 , wherein:
the second value has the predetermined format comprising a first bit, and two or more second bits to represent a value of zero or 2 m wherein m is an integer greater than or equal to zero, and
performing the multiplication of the first value and the second value further comprises:
when the two or more second bits of the first value represent the value of 2 n and the two or more second bits of the second value represent the value of 2 m , shifting, by the shift circuitry, the value of 2 m+1 by (n+1) bits to provide a third multiplication result,
based on a value of the first bit of the second value, selectively outputting zero or the value of 2 n+1 to provide a fourth multiplication result,
based on the value of the first bit of the first value, selectively outputting zero or the value of 2 m+1 to provide a fifth multiplication result,
based on the value of the first bit of the first value, selectively outputting zero or the value of the first bit of the second value to provide a sixth multiplication result, and
adding, by the add circuitry, the third to sixth multiplication results to provide a result of the multiplication of the first value and the second value.

16. The method according to claim 11 , wherein “1 1” as the two or more second bits of the first value represents a value of 4.

17. The method according to claim 11 , wherein the first value further comprises a third bit to indicate that the first value is signed or unsigned.

18. The method according to claim 17 , wherein performing the multiplication of the first value and the second value further comprises:
determining a sign of the result of the multiplication of the first value and the second value based on a value of the third bit of the first value.

19. The method according to claim 11 , further comprising:
performing convolution for a first layer of the neural network using weight data and activation data representing an activation function,
wherein the first value represents a value of one of the weight data and the activation data for the first layer of the neural network.

20. The method according to claim 19 , wherein the second value represents a value of the other of the weight data and the activation data for the first layer of the neural network.

Assignees

• Facebook Tech Llc

Inventors

• Venkatesh Ganesh
• Lai Liangzhen
• Chuang Pierce I-Jen
• Li Meng
• Chandra Vikas

Classifications

• G06F2207/4824

  Neural networks · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/5334

  by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product · CPC title

• G06F7/5235

  using indirect methods, e.g. quarter square method, via logarithmic domain · CPC title