System, apparatus and method for power budget distribution for a plurality of virtual machines to execute on a processor

Patent metadata

Field	Value
Publication number	US-10976801-B2
Application number	US-201816136440-A
Country	US
Kind code	B2
Filing date	Sep 20, 2018
Priority date	Sep 20, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

In one embodiment, a processor includes: a plurality of cores to execute instructions, at least some of the plurality of cores to be allocated to a plurality of virtual machines (VMs); and a power controller coupled to the plurality of cores. The power controller may include a power distribution circuit to distribute an energy budget to the at least some of the plurality of cores according to priority information associated with the plurality of VMs. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores to execute instructions, at least some of the plurality of cores to be allocated to a plurality of virtual machines (VMs); and
a power controller coupled to the plurality of cores, the power controller including a power distribution circuit to distribute an energy budget to the at least some of the plurality of cores according to priority information associated with the plurality of VMs, wherein the power controller comprises:
a first level proportional integral derivative (PID) controller to determine the energy budget; and
a plurality of second level PID controllers each associated with one of the plurality of VMs, wherein each of the plurality of second level PID controllers is to determine a target operating frequency for one or more cores associated with a corresponding VM.

2. The processor of claim 1 , wherein the first level PID controller is to operate at a first bandwidth and the plurality of second level PID controllers is to operate at a second bandwidth, the second bandwidth greater than the first bandwidth.

3. The processor of claim 1 , further comprising a first configuration register to store the priority information, the priority information comprising a relative priority of each of the plurality of VMs.

4. The processor of claim 3 , wherein a virtual machine manager is to write the first configuration register and the power distribution circuit is to obtain the priority information from the first configuration register.

5. The processor of claim 4 , wherein the virtual machine manager is to dynamically update the priority information in the first configuration register, and the power controller is to dynamically re-distribute the energy budget to the at least some of the plurality of cores according to the updated priority information.

6. The processor of claim 1 , further comprising a second configuration register to store mapping information to associate the at least some of the plurality of cores with the plurality of VMs.

7. The processor of claim 6 , wherein a virtual machine manager is to write the second configuration register and the power distribution circuit is to obtain the mapping information from the second configuration register.

8. The processor of claim 1 , wherein the power distribution circuit comprises:
the first level PID controller to determine the energy budget based at least in part on a prior energy budget for a prior control window, a power limit for the processor and a power consumption level of the processor;
a radius calculator to calculate a radius based on the energy budget;
a priority determination circuit to determine a power limit for each of the plurality of VMs based at least in part on the radius and the priority information; and
the plurality of second level PID controllers each to determine a target operating frequency for one or more of the at least some of the plurality of cores based at least in part on the power limit for each of the plurality of VMs and mapping information that associates the plurality of VMs with the at least some of the plurality of cores.

9. The processor of claim 8 , wherein each of the plurality of second level PID controllers are integrated in a power domain of the processor including at least one of the at least some of the plurality of cores.

10. The processor of claim 8 , wherein the priority determination circuit is to calculate angle information for each of the plurality of VMs based on the radius and the priority information.

11. The processor of claim 10 , wherein each of the plurality of second level PID controllers is to determine the target operating frequency based on the angle information.

12. At least one non-transitory computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
calculating, in a power controller of a processor, an energy budget for at least a portion of the processor for a control window;
determining a power limit for each of a plurality of virtual machines to execute on the processor for the control window;
determining a radius value for the control window based on the energy budget;
determining angle information for each of the plurality of virtual machines based on the radius value and priority information associated with the plurality of virtual machines; and
controlling an operating parameter for one or more cores of the processor associated with each of the plurality of virtual machines according to the power limit.

13. The at least one non-transitory computer readable storage medium of claim 12 , wherein the method further comprises obtaining the priority information from at least one first configuration register, the at least one first configuration register to store a priority value for each of the plurality of virtual machines, wherein a virtual machine manager is to write the at least one first configuration register based at least in part on quality of service information for the plurality of virtual machines.

14. The at least one non-transitory computer readable storage medium of claim 12 , wherein the method further comprises obtaining mapping information from at least one second configuration register, the at least one second configuration register to store the mapping information to associate the plurality of virtual machines with a plurality of cores of the processor, wherein a virtual machine manager is to write the at least one second configuration register.

15. The at least one non-transitory computer readable storage medium of claim 14 , wherein the method further comprises determining a target operating frequency for the one or more cores associated with each of the plurality of virtual machines based on the power limit and the mapping information.

16. A system comprising:
a system on chip (SoC) including a plurality of cores to execute instructions, at least some of the plurality of cores to be allocated to a plurality of virtual machines (VMs), and a controller coupled to the plurality of cores, the controller including:
a distribution circuit to distribute a budget for a shared resource to the at least some of the plurality of cores according to priority information associated with the plurality of VMs,
a first proportional integral derivative (PID) controller to determine the budget, and
a plurality of second PID controllers each associated with one of the plurality of VMs, wherein each of the plurality of second PID controllers is to determine a target operating frequency for one or more cores associated with a corresponding VM based at least in part on the budget; and

a dynamic random access memory (DRAM) coupled to the SoC.

17. The system of claim 16 , further comprising:
a first configuration register to store the priority information, the priority information comprising a relative priority of each of the plurality of VMs; and
a second configuration register to store mapping information to associate the at least some of the plurality of cores with the plurality of VMs.

Assignees

• Intel Corp

Inventors

• Ananthakrishnan Avinash
• Gupta Nikhil

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title