Differential to single-ended high bandwidth compensator

Patent metadata

Field	Value
Publication number	US-10976764-B2
Application number	US-201916575259-A
Country	US
Kind code	B2
Filing date	Sep 18, 2019
Priority date	Sep 18, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.

First claim

What is claimed is:

1. An apparatus comprising:
one or more bridges where an individual bridge includes a high-side switch and a low-side switch;
one or more inductors coupled to the one or more bridges;
a capacitor coupled to the one or more inductors and to a load; and
a circuitry to receive a voltage of the capacitor, or a divided version of the voltage of the capacitor, and a reference, wherein the circuitry is to generate an output which is to modify a characteristic of a modulation signal, wherein the circuitry comprises a differential to single-ended circuitry and a compensation circuitry coupled to a first output of the differential to single-ended circuitry, wherein a second output of the compensation circuitry is the output of the circuitry, wherein the differential to single-ended circuitry comprises an amplifier having an input coupled to a resistor divider, wherein the resistor divider is to receive the voltage of the capacitor or the divided version of the voltage of the capacitor, wherein the differential to single-ended circuitry has a first input to receive the voltage of the capacitor or the divided version of the voltage of the capacitor, and a second input to receive a ground voltage sensed at the load.

2. The apparatus of claim 1 , wherein the input is a first input, wherein the resistor divider is a first resistor divider, wherein the amplifier comprises:
a second input coupled to second resistor divider, wherein the second resistor divider is to receive a voltage from a ground.

3. The apparatus of claim 2 , wherein an output of the amplifier is coupled to a resistor.

4. The apparatus of claim 3 , wherein the resistor is coupled to the compensation circuitry.

5. The apparatus of claim 4 , wherein compensation circuitry comprises an amplifier having a first input coupled to the resistor, and a second resistor to receive the reference.

6. The apparatus of claim 5 , wherein the compensation circuitry comprises a first feedback path coupled to the first input of the amplifier of the compensation circuitry and an input of the differential to single-ended circuitry, and wherein the input of the differential to single-ended circuitry is to receive the voltage of the capacitor, or the divided version of the voltage of the capacitor.

7. The apparatus of claim 6 , wherein the first feedback path comprises a switch, a resistor coupled in series with the switch, and a capacitor coupled to the input of the differential to single-ended circuitry and to the resistor.

8. The apparatus of claim 7 , wherein the switch when enabled is to bypass the differential to single-ended circuitry.

9. The apparatus of claim 6 , wherein the compensation circuitry comprises a second feedback path between the second output of the compensation circuitry and the first input of the compensation circuitry, wherein the second feedback path comprises:
a resistor;
a first capacitive circuitry coupled in series with the resistor; and
a second capacitive circuitry coupled to the second output of the compensation circuitry and the first input.

10. The apparatus of claim 7 , wherein the first or second capacitive circuitries comprise a pre-charge circuitry, wherein the pre-charge circuitry includes:
a unity gain amplifier coupled to the reference;
a resistor coupled to the output of the unity gain amplifier;
a plurality of capacitors;
a plurality of first switches coupled to the plurality of capacitors, wherein at least one switch of the plurality of switches is to couple the second output of the compensation circuitry with the first input via at least one of the plurality of capacitors; and
a plurality of second switches which is to pre-charge at least one of the plurality of capacitors or to pre-charge the first input.

11. An apparatus comprising:
a bridge including a high-side switch and a low-side switch;
an inductor coupled to the bridge;
a capacitor coupled to the inductor and to a load; and
a compensation circuitry coupled to the capacitor, wherein the compensation circuitry is to mitigate a voltage droop on the capacitor, wherein the compensation circuitry includes a differential to single-ended circuitry coupled to an amplifier, wherein the amplifier is coupled to a capacitive circuitry which is to pre-charge an input of the amplifier, wherein the capacitive circuitry comprises a plurality of switches, wherein at least one switch of the plurality of switches is to couple an output of the amplifier, and wherein the differential to single-ended circuitry has a first input to receive the voltage of the capacitor, and a second input to receive a ground voltage sensed at the load.

12. The apparatus of claim 11 , wherein the compensation circuitry is to receive a voltage of the capacitor, or a version of the voltage of the capacitor, and a reference, and wherein the compensation circuitry is to generate an output, which is to modify a characteristic of a modulation signal, that is to drive the bridge.

13. The apparatus of claim 12 , wherein the amplifier is coupled to an output of the differential to single-ended circuitry, and wherein an output of the amplifier is the output of the compensation circuitry.

14. The apparatus of claim 13 , wherein the amplifier is a first amplifier, and wherein the differential to single-ended circuitry comprises:
a second amplifier having:
a first input coupled to a first resistor divider, wherein the first resistor divider is to receive the voltage of the capacitor, or the version of the voltage of the capacitor; and
a second input coupled to second resistor divider, wherein the second resistor divider is to receive a voltage from a ground.

15. The apparatus of claim 14 , wherein the plurality of switches is a first plurality of switches, wherein the capacitive circuitry comprises:
a unity gain amplifier coupled to a reference;
a resistor coupled to the output of the unity gain amplifier;
a plurality of capacitors coupled to the plurality of first switches,
wherein the at least one switch of the plurality of first switches is to couple the output of the amplifier with a first input of the amplifier via at least one of the plurality of capacitors; and
a plurality of second switches which is to pre-charge at least one of the plurality of capacitors or to pre-charge the first input.

16. A system comprising:
a processor core;
a voltage regulator coupled to the processor core, wherein the voltage regulator comprises:
a bridge including a high-side switch and a low-side switch;
an inductor coupled to the bridge;
a capacitor coupled to the inductor and to the processor core; and
a compensation circuitry coupled to the capacitor, wherein the compensation circuitry is to mitigate a voltage droop on the capacitor, wherein the compensation circuitry includes a differential to single-ended circuitry coupled to an amplifier, wherein the amplifier is coupled to a capacitive circuitry which is to pre-charge an input of the amplifier, wherein the capacitive circuitry comprises a plurality of switches, wherein at least one switch of the plurality of switches is to couple an output of the amplifier, and wherein the differential to single-ended circuitry has a first input to receive the voltage of the capacitor, and a second input to receive a ground voltage sensed at the processor core; and
a wireless interface to allow the processor core to communicate with another device.

17. The system of claim 16 , wherein the plurality of switches is a first plurality of switches, wherein the capacitive circuitry comprises:
a unity gain amplifier co

Assignees

• Intel Corp

Inventors

• Rodriguez Sergio Carlo
• Lyakhov Alexander
• Schrom Gerhard
• Hodgson Keith
• Makala Sarath S
• Roy Sidhanto

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M3/157

  with digital control · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title