Successive-approximation analog-to-digital converter gain calibration using floating capacitors

Patent metadata

Field	Value
Publication number	US-10972118-B1
Application number	US-202016856204-A
Country	US
Kind code	B1
Filing date	Apr 23, 2020
Priority date	Apr 23, 2020
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

First claim

What is claimed is:

1. A successive-approximation analog-to-digital converter (ADC) comprising:
an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion;
a gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion; and
a charge-redistribution digital-to-analog converter (DAC) comprising a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion of the sampled input charge, a remaining portion of the sampled input charge stored on the input capacitance, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of a third phase of the analog-to-digital conversion, the gain tuning capacitance sequestering the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

2. The successive-approximation ADC as recited in claim 1 , wherein the gain tuning capacitance applies an attenuation to a first range of the input capacitance to match a second range of the charge-redistribution DAC.

3. The successive-approximation ADC as recited in claim 1 , further comprising:
an input capacitor DAC configured to provide the input capacitance according to an input division code corresponding to a ratio of capacitance coupled to the input analog signal during sampling to a total available sampling capacitance.

4. The successive-approximation ADC as recited in claim 3 , wherein the charge-redistribution DAC comprises low voltage transistors and the input capacitor DAC comprises high voltage transistors.

5. The successive-approximation ADC as recited in claim 1 , further comprising:
a gain tuning capacitor DAC configured to provide the gain tuning capacitance corresponding to a gain calibration code.

6. The successive-approximation ADC as recited in claim 1 , further comprising:
a gain tuning capacitor DAC configured to provide the gain tuning capacitance based on a gain calibration code, the gain calibration code corresponding to a value of the gain tuning capacitance that matches an input voltage range to an internal voltage range of the charge-redistribution DAC.

7. The successive-approximation ADC as recited in claim 6 , wherein the input capacitance comprises first unit capacitances greater than second unit capacitances of the charge-redistribution DAC.

8. The successive-approximation ADC as recited in claim 1 , further comprising:
a storage register;
a comparator configured to generate a digital bit signal corresponding to a comparison of a signal on the first node to a second signal on a second node; and
control logic configured to generate switch control signals for sequentially configuring the successive-approximation ADC in the first phase, the second phase, and the third phase to generate the digital output code approximating the input analog signal in response to a clock signal and further configured to store successive values of the digital bit signal in the storage register in the third phase.

9. The successive-approximation ADC as recited in claim 1 ,
wherein the input capacitance comprises a plurality of sampling capacitors, each sampling capacitor having a first plate coupled to the first node and a second plate selectively coupled to an input node and selectively coupled to a ground node according to an input division code;
wherein the gain tuning capacitance comprises a plurality of gain tuning capacitors, each gain tuning capacitor having a third plate coupled to the first node and a fourth plate selectively coupled to a common mode voltage node and selectively coupled to the ground node according to a gain calibration code; and
wherein the charge-redistribution DAC comprises a plurality of conversion capacitors, each conversion capacitor of the plurality of conversion capacitors having a fifth plate coupled to the first node and a sixth plate selectively coupled to a reference voltage node and selectively coupled to the ground node according to the digital output code.

10. The successive-approximation ADC as recited in claim 1 ,
wherein the gain tuning capacitance comprises coarse gain tuning capacitors corresponding to most-significant bits of a gain calibration and fine gain tuning capacitors corresponding to least-significant bits of the gain calibration, and
wherein the coarse gain tuning capacitors are configured to float during the third phase of the analog-to-digital conversion.

11. A method for operating a successive-approximation analog-to-digital converter (ADC) comprising:
storing a sampled input charge on a sampling capacitance coupled to a first node based on an input analog signal during a first phase of an analog-to-digital conversion;
storing a first portion of the sampled input charge on a gain tuning capacitance coupled to the first node during a second phase of the analog-to-digital conversion;
storing a second portion of the sampled input charge on a conversion capacitance of a charge-redistribution digital-to-analog converter (DAC) during the second phase;
sequestering the first portion of the sampled input charge from the charge-redistribution DAC during a third phase of the analog-to-digital conversion; and
converting a digital output code to an analog signal on the first node using the second portion of the sampled input charge, a remaining portion of the sampled input charge stored on the sampling capacitance, and a reference voltage, at an end of the third phase, the digital output code approximating the input analog signal.

12. The method, as recited in claim 11 , wherein the sequestering applies a gain to a first range of the sampling capacitance to match a second range of the charge-redistribution DAC.

13. The method, as recited in claim 11 , further comprising:
controlling an input capacitor DAC to provide the sampling capacitance using high voltage switches;
controlling a gain tuning capacitor DAC to provide the gain tuning capacitance using first low voltage switches; and
controlling the charge-redistribution DAC using second low-voltage switches.

14. The method, as recited in claim 11 , further comprising:
providing the gain tuning capacitance based on a gain calibration code, the gain calibration code corresponding to a value of the gain tuning capacitance that matches an input voltage range of an input capacitor DAC including the sampling capacitance to an internal voltage range of the charge-redistribution DAC.

15. The method, as recited in claim 11 , further comprising:
providing the sampling capacitance based on an input division code corresponding to a ratio of the sampling capacitance to total capacitance available to sample the input analog signal.

16. The method, as recited in claim 15 , wherein the sampling capacitance comprises first unit capacitances greater than second unit capacitances of the charge-redistribution DAC.

17. The method, as recited in claim 15 , further comprising:
generating a digital bit signal corresponding to a comparison of a signal on the first node and a second signal on a second node in the third phase;
storing successive values of the digital bit signal in the third phase; and
generating switch control signals for sequentially configuring the successive-approximation ADC in the first phase, the second phase, and the third phase in respon

Assignees

• Silicon Lab Inc

Inventors

• Abu Hilal Obaida Mohammed Khaled

Classifications

• H03M1/804

  with charge redistribution · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/1009

  Calibration · CPC title