Multilayer ceramic capacitor and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-10971302-B2
Application number	US-201916438272-A
Country	US
Kind code	B2
Filing date	Jun 11, 2019
Priority date	Jun 19, 2018
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: a relationship “M≥−0.00002×EM+0.0012” is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [μm] and a ratio of Mo [atm %] to a B site element [atm %] of a main component ceramic in the end margins is M, wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a multilayer chip having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and each of the plurality of internal electrode layers is alternately exposed to two end faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic; and
a pair of external electrodes that are formed on the two end faces;
wherein:
the pair of external electrodes have a structure in which a plated layer is formed on a ground layer of which a main component is a metal or an alloy including at least one of Ni and Cu;
the ground layer includes Mo; and
wherein a relationship “M≥−0.00002×EM+0.0012” is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [μm] and a ratio of Mo [atm %] to a B site element [atm %] of a main component ceramic in the end margins is M,
wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip,
wherein a concentration of Mo of the ground layer is higher than that of the end margin.

2. The multilayer ceramic capacitor as claimed in claim 1 , wherein the plated layer includes a Sn-plated layer.

3. The multilayer ceramic capacitor as claimed in claim 1 , wherein a main component metal of the ground layer is Ni.

4. The multilayer ceramic capacitor as claimed in claim 1 , wherein a main component of the internal electrode layer is Ni.

5. The multilayer ceramic capacitor as claimed in claim 1 , wherein the length EM of the end margin region is less than 60 μm.

6. The multilayer ceramic capacitor as claimed in claim 1 , wherein the Mo concentration is measured by emitting a laser light to whole of the end margin in a cross section parallel with a side face of the multilayer chip and performing an ICP-MS analysis.

7. The multilayer ceramic capacitor as claimed in claim 1 , wherein the ground layer includes a glass component or a ceramic component.

8. The multilayer ceramic capacitor as claimed in claim 1 , wherein Mo in the ground layer exists in a phase of Mo oxide.

9. A manufacturing method of a ceramic multilayer capacitor comprising:
forming a ceramic multilayer structure having a parallelepiped shape in which each of a plurality of ceramic dielectric green sheets and each of a plurality of conductive pastes for forming an internal electrode are alternately stacked and the each of the plurality of conductive pastes is alternately exposed to two end faces of the ceramic multilayer structure;
coating metal paste on the two end faces, the metal paste contacting to the two end faces, the metal paste including metal powder and a Mo source, a main component of the metal powder being a metal or an alloy including at least one of Ni and Cu;
forming a multilayer chip from the ceramic multilayer structure and ground layers from the metal paste, by firing the ceramic multilayer structure on which the metal paste is coated; and
forming external electrodes, each of which includes each of the ground layers and a plated layer, by performing plating with respect to the ground layers,
wherein an amount of the Mo source in the metal paste is adjusted so that a relationship “M≥−0.00002×EM+0.0012” is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [μm] and a ratio of Mo [atm %] to a B site element [atm %] of a main component ceramic in the end margins is M,
wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip.

Assignees

• Taiyo Yuden Kk

Inventors

• Yanagisawa Atsuhiro
• Shibata Yoshinori
• Tahara Mikio

Classifications

• H01G4/1245

  containing also titanates · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/0085

  Fried electrodes · CPC title

• H01G4/1227 Primary

  based on alkaline earth titanates · CPC title