Power-based dynamic adjustment of memory module bandwidth

Patent metadata

Field	Value
Publication number	US-10969974-B2
Application number	US-201816112461-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A memory controller includes a sensor poller and a proportional integral controller (PIC) coupled to the sensor poller. The sensor poller is to obtain a temperature and a power of a memory module (MM) operated by the controller, and the PIC is to: dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM. The dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit. A system includes a memory controller and a dual in-line memory module (DIMM) operated by it.

First claim

What is claimed is:

1. A memory controller (MC), comprising:
a sensor poller to obtain a temperature and a power of a memory module (MM) operated by the MC; and
a proportional integral controller (PIC), coupled to the sensor poller, to:
dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM,
wherein the dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit (Tlimit),
wherein the PIC uses an algorithm comprising two nested PI control loops to set the at least one bandwidth limit.

2. The MC of claim 1 , wherein the at least one bandwidth limit is one or both of:
a maximum column access strobe (CAS) rate performed by the MM, or a maximum row activation (ACT) rate performed by the MM.

3. The MC of claim 1 , wherein the MM is a DDR5 dual in-line memory module (DIMM).

4. The MC of claim 1 , wherein the sensor poller is further to periodically obtain at least one temperature of the MM and at least one power of the MM to dynamically set the at least one bandwidth limit.

5. The MC of claim 4 , wherein the at least one temperature and the at least one power are each read out of at least one register of the MM.

6. The MC of claim 4 , wherein the temperature is a maximum temperature of the MM and the power is an average total power of the MM, each read out of a register of a data consolidation hub of the MM.

7. The MC of claim 1 , wherein the nested PI control loops include an outer PI control loop that relates a power of the MM to Tlimit, and an inner control loop that relates a bandwidth limit variable to the power of the MM.

8. The MC of claim 1 , wherein:
the sensor poller is further to successively obtain each of the temperature and the power of the MM at a pre-defined sample rate, and
the PIC is further to set the at least one bandwidth limit to obtain a running average power value of the MM equal to a power set point that is dynamically determined by the algorithm.

9. The MC of claim 1 , wherein the PIC is further to determine if the temperature of the MM has fallen below a pre-defined temperature below Tlimit, and, in response to the determination, remove the at least one bandwidth limit.

10. The MC of claim 1 , wherein the MM is a DIMM comprising a data consolidation hub coupled to multiple temperature sensors and multiple power rails of the DIMM, the hub storing an average total value of the power rails, and a maximum value of the temperature sensors, wherein:
the sensor poller is further to receive a DIMM maximum temperature from a first register of the data consolidation hub, and a DIMM average total power from a second register of the data consolidation hub, and
the PIC is further to use the temperature and power values received from the data consolidation hub to dynamically set at least one bandwidth limit for the DIMM.

11. One or more non-transitory computer-readable storage media comprising a set of instructions, which, when executed by an MC operating an MM of a computing device, cause the MC to:
obtain a temperature and a power of the MM; and
dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM,
wherein the dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit (Tlimit),
wherein the at least one bandwidth limit is one or both of: a maximum number of column access strobes (CASs) or a maximum number of row activations (ACTs), per unit time.

12. The one or more non-transitory computer-readable storage media of claim 11 , wherein the instructions, when executed, further cause the MC to periodically obtain at least one temperature value of the MM, and at least one power value of the MM, to dynamically set the at least one bandwidth limit.

13. The one or more non-transitory computer-readable storage media of claim 11 , wherein the instructions, when executed, further cause the MC to read each of the temperature and the power of the MM out of a register of the MM.

14. The one or more non-transitory computer-readable storage media of claim 11 , wherein the instructions, when executed, further cause the MC to use an algorithm comprising two nested PI control loops to set the at least one bandwidth limit, wherein the nested PI control loops include an outer PI control loop that relates a power of the MM to Tlimit, and an inner control loop that relates a bandwidth limit variable to the power of the MM.

15. The one or more non-transitory computer-readable storage media of claim 14 , wherein the instructions, when executed, further cause the MC to:
set the at least one bandwidth limit to obtain a running average power of the MM equal to a power set point dynamically determined by the algorithm.

16. A system, comprising:
an MM; and
a PIC to thermally manage the MM, the PIC to:
dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM,
wherein the dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit (Tlimit), wherein:
the at least one bandwidth limit is one or both of: a maximum column access strobe (CAS) rate performed by the MM, or a maximum row activation (ACT) rate performed by the MM, and wherein the PIC uses an algorithm comprising two nested PI control loops to set the at least one bandwidth limit.

17. The system of claim 16 , wherein the nested PI control loops include an outer PI control loop that relates a power of the MM to Tlimit, and an inner control loop that relates a bandwidth limit variable to the power of the MM.

Assignees

• Intel Corp

Inventors

• Vergis George
• Heymann Douglas
• Le Dat
• Goles John

Classifications

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F3/0629 Primary

  Configuration or reconfiguration of storage systems · CPC title