Latency synchronization across clock domains

Patent metadata

Field	Value
Publication number	US-10969821-B2
Application number	US-201815991179-A
Country	US
Kind code	B2
Filing date	May 29, 2018
Priority date	May 29, 2018
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

First claim

What is claimed is:

1. A method for tracking delay in signals, the method comprising:
at a first time, receiving a common timing reference signal (SysRef) at a transmitter on a first clock domain, and inputting, in response to the SysRef and a clock signal of the transmitter, a latency marker into a first-in first-out data structure (FIFO) coupling the first clock domain to a second clock domain;
at a second time, receiving the SysRef at a receiver on a second clock domain, and starting a counter at the second clock domain in response to the SysRef and a clock signal of the receiver, wherein the first clock domain differs from the second clock domain;
at a third time, receiving the latency marker from the FIFO at the second clock domain and stopping the counter at a final count; and
determining a FIFO latency based on the final count and on a difference between the second time and the first time.

2. The method of claim 1 , further comprising, synchronizing one or more events on the first clock domain and the second clock domain based at least in part on the latency marker.

3. The method of claim 2 , wherein a data converter is on the second clock domain, and synchronizing the one or more events comprises, at the third time, passing the latency marker with a data flow to the data converter.

4. The method of claim 1 , further comprising selectively adjusting a read pointer of the FIFO based at least in part on the FIFO latency.

5. The method of claim 4 , wherein the read pointer of the FIFO is selectively adjusted based at least in part on a comparison of the FIFO latency to a clock domain latency associated with a third clock domain coupled to the first clock domain.

6. The method of claim 5 , wherein selectively adjusting the read pointer comprises positively offsetting the read pointer in response to determining that the FIFO latency is less than the clock domain latency.

7. The method of claim 5 , wherein selectively adjusting the read pointer comprises negatively offsetting the read pointer in response to determining that the FIFO latency is greater than the clock domain latency.

8. The method of claim 1 , further comprising:
writing a first number of words to the FIFO for each cycle of a write clock associated with the first clock domain, and reading a second number of words from the FIFO for each cycle of a read clock associated with the second clock domain;
wherein the latency marker input into the FIFO is input at a predetermined word within a cycle of the write clock; and
wherein determining the FIFO latency is further based on the second number of words and a position of the predetermined word.

9. A latency determination circuit, comprising:
a transmitter on a first clock domain;
a receiver on a second clock domain, the receiver comprising a counter; and
a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain, wherein the first clock domain differs from the second clock domain;
wherein the transmitter is configured to, at a first time, receive a common timing reference signal (SysRef) and input, in response to the SysRef and a clock signal of the transmitter, a latency marker into the FIFO; and
wherein the receiver is configured to:
at a second time, receive the SysRef, and start the counter in response to the SysRef and a clock signal of the receiver;
at a third time, receive the latency marker from the FIFO and stop the counter at a final count; and
determine a FIFO latency based on the final count and on a difference between the second time and the first time.

10. The latency determination circuit of claim 9 , wherein the receiver is further configured to synchronize one or more events on the first clock domain and the second clock domain based at least in part on the latency marker.

11. The latency determination circuit of claim 10 , wherein the receiver comprises a data converter, and wherein synchronizing the one or more events comprises, at the third time, passing the latency marker with a data flow to the data converter.

12. The latency determination circuit of claim 9 , wherein the receiver is further configured to selectively adjust a read pointer of the FIFO based at least in part on the FIFO latency.

13. The latency determination circuit of claim 12 , wherein the read pointer of the FIFO is selectively adjusted based at least in part on a comparison of the FIFO latency to a clock domain latency associated with a third clock domain coupled to the first clock domain.

14. The latency determination circuit of claim 13 , wherein the read pointer is selectively adjusted by positively offsetting the read pointer in response to determining that the FIFO latency is less than the clock domain latency.

15. The latency determination circuit of claim 13 , wherein the read pointer is selectively adjusted by negatively offsetting the read pointer in response to determining that the FIFO latency is greater than the clock domain latency.

16. The latency determination circuit of claim 9 , wherein:
the transmitter is further configured to write a first number of words to the FIFO for each cycle of a write clock associated with the first clock domain, and the latency marker is input into the FIFO at a predetermined word within a cycle of the write clock;
the receiver is further configured to read a second number of words from the FIFO for each cycle of a read clock associated with the second clock domain, and to determine the FIFO latency based at least in part on the second number of words and a position of the predetermined word.

17. A latency determination circuit, comprising:
one or more processors; and
a memory storing instructions that, when executed by the one or more processors, cause the latency determination circuit to perform operations comprising:
at a first time, receiving a common timing reference signal (SysRef) at a first clock domain, and inputting, in response to the SysRef and a clock signal of a transmitter on the first clock domain, a latency marker into a first-in first-out data structure (FIFO) coupling the first clock domain to a second clock domain;
at a second time, receiving the SysRef at the second clock domain, and starting, in response to the SysRef and a clock signal of a receiver on the second clock domain, a counter at the second clock domain, wherein the second clock domain differs from the first clock domain;
at a third time, receiving the latency marker from the FIFO at the second clock domain and stopping the counter at a final count; and
determining a FIFO latency based on the final count and on a difference between the second time and the first time.

18. The latency determination circuit of claim 17 , wherein execution of the instructions causes the latency determination circuit to perform operations further comprising synchronizing one or more events on the first clock domain and the second clock domain based at least in part on the latency marker.

19. The latency determination circuit of claim 18 , wherein the instructions which execute to synchronize the one or more events causes the latency determination circuit to perform operations further comprising, at the third time, passing the latency marker with a data flow to a data converter on the second clock domain.

20. The latency determination circuit of claim 17 , wherein execution of the instructions causes the latency determination circuit to perform operations further comprising selectively adjusting a read pointer of the FIFO based at least in part on

Assignees

• Xilinx Inc

Inventors

• Kinnerk Ryan
• Verbruggen Bob W
• Mcgrath John E

Classifications

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title