Array substrate, display panel and display device for improving alignment defects

Patent metadata

Field	Value
Publication number	US-10969639-B2
Application number	US-201816096474-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 23, 2017
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

Provided is an array substrate including gate lines, data lines, and a first alignment layer above a layer where the gate lines are located and a layer where the data lines are located, the gate lines and the data lines being arranged to intersect with each other to divide the array substrate into pixel regions. Each pixel region includes first and second sides opposite to each other and third and fourth sides opposite to each other, each of the first and second sides connecting the third side to the fourth side and extending in one direction, lengths of the first and second sides being greater than lengths of the third and fourth sides, the first alignment layer having a first alignment direction, and each of the first and second sides forming an acute angle with the first alignment direction. A display panel and a display device are also provided.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of gate lines, a plurality of data lines, and a first alignment layer disposed above a layer where the gate lines are located and a layer where the data lines are located, the gate lines and the data lines being arranged to intersect with each other to divide the array substrate into a plurality of pixel regions in rows and columns,
wherein each of the pixel regions comprises a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, each of the first side and the second side connects the third side to the fourth side, and both of the first side and the second side extend in one direction, lengths of the first side and the second side are greater than lengths of the third side and the fourth side, the first alignment layer has a first alignment direction, and for each of the pixel regions, an angle from each of the first side and the second side to the first alignment direction in a clockwise direction is an acute angle, and pixel regions adjacent in a column direction are staggered such that the first sides of the pixel regions adjacent in the column direction are non-collinear, and
wherein each of the pixel regions is provided therein with a pixel electrode, and the pixel electrode comprises at least two sub-electrode portions arranged along the first alignment direction, each of the sub-electrode portions is provided with a plurality of slits and the slits of two adjacent sub-electrode portions of each of the pixel electrodes have different extending directions.

2. The array substrate of claim 1 , wherein the plurality of pixel regions are arranged in a plurality of rows, the gate lines extend in a row direction, and the first alignment direction is perpendicular to the row direction.

3. The array substrate of claim 2 , wherein an extending direction of a portion of each of the plurality of data lines between two adjacent pixel regions in a same row is substantially the same as an extending direction of at least one of the first side and the second side of the pixel region.

4. The array substrate of claim 1 , wherein an angle between at least one of the first side and the second side of the pixel region and the first alignment direction is in a range of about 10° to about 25°.

5. The array substrate of claim 4 , wherein an extending direction of a portion of each of the plurality of data lines between two adjacent pixel regions in a same row is substantially the same as an extending direction of at least one of the first side and the second side of the pixel region.

6. The array substrate of claim 1 , wherein an extending direction of a portion of each of the plurality of data lines between two adjacent pixel regions in a same row is substantially the same as an extending direction of at least one of the first side and the second side of the pixel region.

7. The array substrate of claim 1 , wherein an angle between the extending direction of the slits of each of the sub-electrode portions and the first alignment direction is identical.

8. The array substrate of claim 1 , wherein an angle between the extending direction of the slits of each of the sub-electrode portions and the first alignment direction is in a range of about 5° to about 20°.

9. A display panel, comprising the array substrate of claim 1 and a counter substrate arranged opposite to and aligned with the array substrate, wherein the counter substrate comprises a second alignment layer at a side of the counter substrate facing the array substrate, and the second alignment layer has a second alignment direction forming an acute angle with each of the first side and the second side of the pixel region.

10. The display panel of claim 9 , wherein the plurality of pixel regions are arranged in a plurality of rows, and the counter substrate further comprises color filter blocks arranged in one-to-one correspondence with the pixel regions, the color filter blocks including color filter blocks of n colors, n being an integer greater than or equal to 3,
n adjacent color filter blocks in a same row have colors different from each other, and
in n rows of color filter blocks arranged sequentially, n color filter blocks respectively from the n rows and having corresponding positions in respective rows have colors different from each other, the color filter blocks having corresponding position in respective rows being color filter blocks having a same sequence number in the n rows in a case where the color filter blocks in each of the n rows are numbered in a same direction.

11. A display device, comprising the display panel of claim 9 .

12. A display device, comprising the display panel of claim 10 .

13. The array substrate of claim 1 , for each pixel region, angles between the extending directions of the slits of two adjacent sub-electrode portions of the pixel electrode in the pixel region and the first side of the pixel region are different.

14. An array substrate, comprising a plurality of gate lines, a plurality of data lines, and a first alignment layer disposed above a layer where the gate lines are located and a layer where the data lines are located, the gate lines and the data lines being arranged to intersect with each other to divide the array substrate into a plurality of pixel regions in rows and columns,
wherein each of the pixel regions comprises a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, each of the first side and the second side connects the third side to the fourth side, and both of the first side and the second side extend in one direction, lengths of the first side and the second side are greater than lengths of the third side and the fourth side, the first alignment layer has a first alignment direction, and for each of the pixel regions, an angle from each of the first side and the second side to the first alignment direction in a clockwise direction is an acute angle, and
wherein an extending direction of a portion of each of the plurality of data lines between two rows of pixel regions is different from the one direction in which the first side and the second side extend such that the data lines are bent, and one of the data lines between a first row of pixel regions and a second row of pixel regions is bent in a direction that is opposite to a direction in which one of the data lines between the second row of pixel regions and a third row of pixel regions is bent, the first row being adjacent to the second row, and the second row being adjacent to the third row.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Wang Wenhao
• Hong Yanping
• Liao Weijing
• Jing Hui
• Ruan Defa

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F2201/123

  pixel · CPC title