Systems and methods for facilitating data encryption and decryption and erasing of associated information

Patent metadata

Field	Value
Publication number	US-10965456-B2
Application number	US-201715714948-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 25, 2017
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Various techniques provide systems and methods for facilitating data encryption/decryption and almost immediate erasure of associated information. In one example, a method includes receiving first data in a first memory. The method further includes receiving a first key in a second memory. The method further includes generating, by a logic circuit, second data based on the first data and the first key. The method further includes providing the second data for transmission. The method further includes erasing the first data and/or the first key in one-half clock cycle of generating the second data. Related methods and devices are also provided.

First claim

What is claimed is:

1. A method comprising:
receiving first data in a plurality of memory cells of a first memory;
receiving a first key in a plurality of memory cells of a second memory;
generating, by a logic circuit, second data based on the first data and the first key;
providing the second data for transmission;
erasing the first key in one-half clock cycle of generating the second data by overwriting the plurality of memory cells of the second memory; and
receiving a second key in the plurality of memory cells of the second memory.

2. The method of claim 1 , wherein the erasing further comprises erasing the first data.

3. The method of claim 2 , wherein the erasing comprises:
erasing the first data in the plurality of memory cells of the first memory by overwriting the plurality of memory cells of the first memory with results of bitwise operations on the first data, first key, and second data; and
erasing the first key in the plurality of memory cells of the second memory by overwriting the plurality of memory cells of the second memory with results of bitwise operations on the first data, first key, and second data.

4. The method of claim 1 , wherein the erasing comprises providing, by the logic circuit, information associated with the second data to the plurality of memory cells of the second memory to overwrite the second memory.

5. The method of claim 4 , wherein the information is a scrambled version of the second data.

6. The method of claim 1 , wherein the erasing comprises erasing the first key in the second memory by overwriting the plurality of memory cells of the second memory with a predetermined bit sequence.

7. The method of claim 1 , further comprising:
receiving third data in the plurality of memory cells of the first memory;
generating, by the logic circuit, fourth data by performing bitwise operations to combine each bit of the third data with a corresponding bit of the second key;
providing the fourth data for transmission; and
erasing the second key within one-half clock cycle of generating the fourth data.

8. The method of claim 1 , wherein the providing comprises storing the second data in a third memory and transmitting the second data to a device, wherein the generating comprises performing bitwise operations to combine each bit of the first data with a corresponding bit of the first key, and wherein the first data is plaintext data, the first key is an encryption key, and the second data is encrypted data.

9. The method of claim 1 , wherein the first data is encrypted data, the first key is a decryption key, and the second data is decrypted data.

10. The method of claim 1 , wherein the first data, second data, and first key have the same length.

11. The method of claim 1 , wherein:
the receiving the first data comprises receiving a first data bit in a first memory cell of the plurality of memory cells of the first memory;
the receiving the first key comprises receiving a first key bit in a first memory cell of the plurality of memory cells of the second memory;
the generating comprises generating a second data bit based on the first data bit and the first key bit;
the providing comprises providing the second data bit for transmission;
the erasing comprises erasing the first key bit in one-half clock cycle of generating the second data bit by overwriting the first memory cell of the plurality of memory cells of the second memory; and
the receiving the second key comprises receiving a second key bit in a second memory of the plurality of memory cells of the second memory.

12. A device comprising:
a logic circuit configured to generate second data based on first data and a first key;
a first memory configured to receive the first data; and
a second memory configured to:
receive the first key in a plurality of memory cells of the second memory;
receive values to overwrite the first key in one-half clock cycle of generation of the second data; and
receive a second key in the plurality of memory cells subsequent to overwriting of the first key.

13. The device of claim 12 , wherein the second memory is configured to receive, in the plurality of memory cells of the second memory, values that are results of bitwise operations on the first data and first key from the logic circuit, wherein the received values overwrite the first key.

14. The device of claim 12 , wherein the second memory is configured to receive, in the plurality of memory cells of the second memory, a predetermined bit sequence to overwrite the first key.

15. The device of claim 12 , wherein the first memory is further configured to receive values to overwrite the first data in one-half clock cycle of generation of the second data.

16. The device of claim 12 , wherein:
the logic circuit is further configured to generate fourth data based on third data and the second key;
the first memory is further configured to receive the third data; and
the second memory is further configured to:
receive values to overwrite the second key in one-half clock cycle of generation of the fourth data.

17. The device of claim 12 , further comprising a shift register configured to receive the second data and shift out the second data to provide the second data for transmission, wherein the first data is plaintext data, the first key is an encryption key, and the second data is encrypted data, and wherein the logic circuit comprises a plurality of bitwise operator circuits.

18. The device of claim 12 , wherein the first data is encrypted data, the first key is a decryption key, and the second data is decrypted data.

19. The device of claim 17 , wherein the first memory comprises a first shift register and the second memory comprises a second shift register.

20. The device of claim 19 , wherein the second shift register does not permit serial outshift capability, such that the first key is prevented from being provided via a serial shift out path.

Assignees

• Boeing Co

Inventors

• Hunt Jeffrey H
• Howe Wayne R

Classifications

• H04L9/0656

  Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher · CPC title

• H04L9/0891 Primary

  Revocation or update of secret information, e.g. encryption key update or rekeying · CPC title

• H04L9/14

  using a plurality of keys or algorithms · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0671

  In-line storage system · CPC title