Normal incidence photodetector with self-test functionality
US-2020162156-A1 · May 21, 2020 · US
US10965369B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10965369-B2 |
| Application number | US-202016854012-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 21, 2020 |
| Priority date | Nov 20, 2018 |
| Publication date | Mar 30, 2021 |
| Grant date | Mar 30, 2021 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Photonically integrated normal incidence photodetectors (NIPDs) and associated in-plane waveguide structures optically coupled to the NIPDs can be configured to allow for both in-plane and normal-incidence detection. In photonic circuits with light-generation capabilities, such as integrated optical transceivers, the ability of the NIPDs to detect in-plane light is used, in accordance with some embodiments, to provide self-test functionality.
Opening claim text (preview).
What is claimed is: 1. A photodetector structure comprising: a circular, oval, or square-shaped p-i-n mesa bonded to a semiconductor device layer of a semiconductor-on-insulator (SOI) substrate comprising the semiconductor device layer on top of an insulating undercladding, the p-i-n mesa comprising n-type, active, and p-type semiconductor layers; metal contacts contacting the p-type and n-type semiconductor layers; and a semiconductor waveguide formed in the semiconductor device layer of the SOI substrate and configured to operatively couple light into the p-i-n mesa. 2. The photodetector structure of claim 1 , wherein the waveguide flares out from a width smaller than half of a diameter of the p-i-n mesa to a strip underneath the p-i-n mesa dimensioned and positioned to encompass at least half the diameter of the p-i-n mesa, the strip operatively to couple light through a bottom surface of the p-i-n mesa into the p-i-n mesa. 3. The photodetector structure of claim 1 , wherein the waveguide comprises a wrap-around portion formed along and underneath an edge of the p-i-n mesa to operatively couple light at least one of directly into the p-i-n mesa or into a semiconductor structure formed in the semiconductor device layer underneath the p-i-n mesa. 4. The photodetector structure of claim 3 , wherein the portion of the waveguide formed along and underneath the edge of the p-i-n mesa tapers down to a narrower width at a terminal end of the waveguide. 5. The photodetector structure of claim 3 , wherein the semiconductor device layer is at least partially etched down in a region underneath the p-i-n mesa surrounded by the wrap-around portion of the waveguide. 6. The photodetector structure of claim 3 , wherein the semiconductor device layer is left unetched in a region underneath the p-i-n mesa surrounded by the wrap-around portion of the waveguide. 7. The photodetector structure of claim 3 , wherein the semiconductor device layer is patterned in accordance with a fill pattern in a region underneath the p-i-n mesa surrounded by the wrap-around portion of the waveguide. 8. The photodetector structure of claim 1 , wherein the p-i-n mesa is made from III-V materials, and wherein the semiconductor device layer and the semiconductor waveguide are made of silicon. 9. An optical transceiver integrated on a semiconductor substrate, the optical transceiver comprising: one or more optical transmitters formed at least in part in a device layer of the substrate; one or more optical receivers each comprising a photodetector formed on the substrate by a p-i-n mesa with electrical connections, and a waveguide formed in a device layer of the substrate and configured to couple light into the p-i-n mesa; and an optical switch configured to selectively either enable or disable a self-test mode, wherein enabling the self-test mode comprises coupling the one or more optical transmitters to the waveguides of the one or more optical receivers. 10. The optical transceiver of claim 9 , comprising multiple optical transmitters and multiple respective optical receivers configured for multiple respective operating wavelengths, wherein the optical switch comprises a wavelength multiplexer further configured to multiplex optical signals received from the multiple optical transmitters. 11. The optical transceiver of claim 9 , wherein the optical switch is configured to selectively enable or disable the self-test mode by selectively focusing an optical signal onto one of two outputs of the optical switch, wherein an output, of the two outputs, that is associated with the self-test mode optically connects the optical switch to the receivers. 12. The optical transceiver of claim 11 , wherein the optical switch comprises an active tuning element configured to change optical path lengths of the optical signal to perform the focusing. 13. The optical transceiver of claim 9 , wherein the optical switch comprises a Mach-Zehnder modulator. 14. The optical transceiver of claim 9 , wherein the waveguide of at least one of the optical receivers flares out from a width smaller than half of a diameter of the p-i-n mesa to a strip underneath the p-i-n mesa dimensioned and positioned to encompass at least half the diameter of the p-i-n mesa, the strip operatively to couple light through a bottom surface of the p-i-n mesa into the p-i-n mesa. 15. The optical transceiver of claim 9 , wherein the waveguide comprises a wrap-around portion formed along and underneath an edge of the p-i-n mesa to operatively couple light at least one of directly into the p-i-n mesa or into a semiconductor structure formed in the semiconductor device layer underneath the p-i-n mesa. 16. The optical transceiver of claim 9 , wherein the photodetector is a normal-incidence photodetector. 17. The optical transceiver of claim 9 , wherein the p-i-n mesa is circular, oval, or square-shaped. 18. A method of testing an optical transceiver comprising an optical transmitter and an optical receiver integrated on a single substrate comprising a semiconductor device layer on top of an insulating undercladding, the optical receiver comprising a normal incidence photodetector (NIPD) bonded to the semiconductor device layer of the substrate and an associated waveguide structure formed in the semiconductor device layer of the substrate underneath the NIPD and configured to couple in-plane light into the NIPD, the method comprising: generating a modulated optical signal with the optical transmitter, the modulated optical signal carrying high-speed data; selectively coupling an output of the optical transmitter to the waveguide structure associated with the NIPD, whereby the optical signal is coupled vertically into the NIPD; and measuring a photocurrent at the NIPD to determine at least one of a bit error rate, a packet loss, a bandwidth, or a responsivity of the receiver. 19. The method of claim 16 , wherein the waveguide structure flares out from a width smaller than half a diameter of the NIPD to a strip underneath the NIPD that encompasses at least half the diameter of the NIPD, and wherein the optical signal is coupled vertically from the strip into the NIPD. 20. The method of claim 16 , wherein the waveguide structure comprises a wrap-around portion formed along and underneath an edge of the NIPD, and wherein the optical signal is coupled at least one of directly vertically into the NIPD or into a semiconductor structure formed underneath the NIPD from which the optical signal is coupled vertically into the NIPD.
directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42) · CPC title
comprising only Group III-V materials, e.g. GaAs · CPC title
the potential barrier being a PIN barrier · CPC title
comprising ring electrodes · CPC title
Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.