Analog-digital converter, solid-state imaging element, and electronic equipment

Patent metadata

Field	Value
Publication number	US-10965301-B2
Application number	US-201816486244-A
Country	US
Kind code	B2
Filing date	Feb 2, 2018
Priority date	Mar 8, 2017
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Included are a loop filter, a quantization circuit section, and a current steering digital-analog conversion section. The quantization circuit section converts a loop filter output into a digital value. The current steering digital-analog conversion section is provided in a feedback loop that feeds back the output of the quantization circuit section to the loop filter. Then, each of the analog-digital converters includes a first input signal current path, a second input signal current path, a first feedback current path, and a second feedback current path. The first input signal current path feeds a first input signal current to an input end of a first stage integrator of the loop filter. The second input signal current path feeds a second input signal current, a current opposite in sign to the first input signal current, to an input end of a second stage integrator of the loop filter. The first feedback current path connects one feedback output end of the current steering digital-analog conversion section to the input end of the first stage integrator of the loop filter. The second feedback current path connects other feedback output end of the current steering digital-analog conversion section to the input end of the second stage integrator of the loop filter.

First claim

The invention claimed is:

1. An analog-digital converter, comprising:
a loop filter having at least two cascaded integrators;
a quantization circuit section configured to convert a loop filter output into a digital value;
a current steering digital-analog conversion section in a feedback loop that feeds back an output of the quantization circuit section to the loop filter, wherein
the current steering digital-analog conversion section includes a first current source, a first switching element, and a second switching element, and
a first end of two ends of the first switching element and a first end of two ends of the second switching element are connected to the first current source;

a first input signal current path configured to feed a first input signal current to an input end of a first stage integrator of the loop filter;
a second input signal current path configured to feed a second input signal current to an input end of a second stage integrator of the loop filter, wherein the second input signal current is opposite in sign to the first input signal current;
a first feedback current path configured to connect a second end of the two ends of the first switching element to the input end of the first stage integrator of the loop filter; and
a second feedback current path configured to connect a second end of the two ends of the second switching element to the input end of the second stage integrator of the loop filter.

2. The analog-digital converter according to claim 1 , wherein the second stage integrator is configured to operate in an inverted mode.

3. The analog-digital converter according to claim 1 , further comprising a voltage-current conversion circuit section configured to supply the first input signal current and the second input signal current at an input stage.

4. The analog-digital converter according to claim 3 , wherein
the voltage-current conversion circuit section includes a second current source configured to feed a bias current, and
a circuit section configured to distribute the bias current as the first input signal current and the second input signal current.

5. The analog-digital converter according to claim 3 , wherein the voltage-current conversion circuit section includes a differential transconductance amplifier.

6. The analog-digital converter according to claim 1 , wherein the loop filter includes an active RC integrator.

7. A solid-state imaging element, comprising:
a pixel array section having unit pixels in a matrix pattern, wherein each of the unit pixels includes a photoelectric conversion section, and the unit pixels are configured to output analog pixel signals; and
a column processing section that includes analog-digital converters configured to convert the analog pixel signals into digital pixel signals, wherein
each of the analog-digital converters includes:
a loop filter having at least two cascaded integrators;
a quantization circuit section configured to convert a loop filter output into a digital value;
a current steering digital-analog conversion section in a feedback loop that feeds back an output of the quantization circuit section to the loop filter, wherein
the current steering digital-analog conversion section includes a first current source, a first switching element, and a second switching element; and
a first end of two ends of the first switching element and a first end of two ends of the second switching element are connected to the first current source;

a first input signal current path configured to feed a first input signal current to an input end of a first stage integrator of the loop filter;
a second input signal current path configured to feed a second input signal current to an input end of a second stage integrator of the loop filter, wherein the second input signal current is opposite in sign to the first input signal current;
a first feedback current path configured to connect a second end of the two ends of the first switching element to the input end of the first stage integrator of the loop filter; and
a second feedback current path configured to connect a second end of the two ends of the second switching element to the input end of the second stage integrator of the loop filter.

8. The solid-state imaging element according to claim 7 , wherein the second stage integrator is configured to operate in an inverted mode.

9. The solid-state imaging element according to claim 7 , further comprising a voltage-current conversion circuit section configured to supply the first input signal current and the second input signal current at an input stage.

10. The solid-state imaging element according to claim 9 , wherein
the voltage-current conversion circuit section includes a second current source configured to feed a bias current, and
a circuit section configured to distribute the bias current as the first input signal current and the second input signal current.

11. The solid-state imaging element according to claim 9 , wherein the voltage-current conversion circuit section includes a differential transconductance amplifier.

12. The solid-state imaging element according to claim 11 , wherein
each of the unit pixels further includes a charge accumulation section, and
a reset level at a time of reset of the charge accumulation section and a signal level at a time of photoelectric conversion with a photoelectric conversion element of the photoelectric conversion section are output as the analog pixel signals.

13. The solid-state imaging element according to claim 7 , wherein the loop filter includes an active RC integrator.

14. An electronic equipment, comprising:
a solid-state imaging element, the solid-state imaging element including:
a pixel array section having unit pixels in a matrix pattern, wherein
each of the unit pixels includes a photoelectric conversion section, and
the unit pixels are configured to output analog pixel signals; and

a column processing section that includes analog-digital converters configured to convert the analog pixel signals into digital pixel signals, wherein
each of the analog-digital converters includes:
a loop filter having at least two cascaded integrators;
a quantization circuit section configured to convert a loop filter output into a digital value;
a current steering digital-analog conversion section in a feedback loop that feeds back an output of the quantization circuit section to the loop filter, wherein
the current steering digital-analog conversion section includes a first current source, a first switching element, and a second switching element, and
a first end of two ends of the first switching element and a first end of two ends of the second switching element are connected to the first current source;

a first input signal current path configured to feed a first input signal current to an input end of a first stage integrator of the loop filter;
a second input signal current path configured to feed a second input signal current to an input end of a second stage integrator of the loop filter, wherein the second input signal current is opposite in sign to the first input signal current;
a first feedback current path configured to connect a second end of the two ends of the first switching element to the input end of the first stage integrator of the loop filter; and
a second feedback current path configured to connect a second end of the two ends of the second switching element to the input end of the second stage integrator of the loop filter.

15. The electronic equipment according to claim 14 , wherein the second stage integrator is configured to

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Moue Takashi
• Matsumoto Takashi

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H03M3/484

  by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path · CPC title

• H03M3/438 Primary

  the modulator having a higher order loop filter in the feedforward path · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title