Single material electronic device and method of producing such an electronic device

Patent metadata

Field	Value
Publication number	US-10964822-B2
Application number	US-201816624151-A
Country	US
Kind code	B2
Filing date	Jun 15, 2018
Priority date	Jul 18, 2017
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A semiconductor device includes a substrate, a gate arranged on the substrate, a dielectric arranged on the gate, a channel arranged on the dielectric, a source electrically coupled to the channel, and a drain electrically coupled to the channel. Each of the gate, dielectric, channel, source, and drain includes a corresponding mixture of hafnium dioxide (HfCte) and zinc oxide (ZnO) layers and at least two of the gate, dielectric, channel, source, and drain comprise different mixtures of the hafnium dioxide and zinc oxide layers.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a gate arranged on the substrate;
a dielectric arranged on the gate;
a channel arranged on the dielectric;
a source electrically coupled to the channel; and
a drain electrically coupled to the channel,
wherein each of the gate, dielectric, channel, source, and drain comprises a corresponding mixture of hafnium dioxide (HfO 2 ) and zinc oxide (ZnO) layers and at least two of the gate, dielectric, channel, source, and drain comprise different mixtures of the hafnium dioxide and zinc oxide layers.

2. The semiconductor device of claim 1 , wherein the dielectric, gate, source, and drain each comprise a layer of zinc oxide on top of a plurality of layers of hafnium dioxide.

3. The semiconductor device of claim 2 , wherein the dielectric includes fewer layers of hafnium dioxide than the gate, source, and drain.

4. The semiconductor device of claim 1 , wherein the channel comprises a plurality of layers of hafnium dioxide on top of a plurality of layers of zinc oxide.

5. The semiconductor device of claim 1 , wherein
the gate, source, and drain each comprise a first set of layers of zinc oxide and hafnium dioxide;
the dielectric comprises a second set of layers of zinc oxide and hafnium dioxide,
the channel comprises a third set of layers of hafnium dioxide and zinc oxide,
the first and second set of layers include more layers of hafnium dioxide than zinc oxide, and
the third set of layers include more layers of zinc oxide than hafnium oxide.

6. The semiconductor device of claim 1 , wherein the electronic device is substantially transparent.

7. The semiconductor device of claim 1 , wherein the gate, dielectric, channel, source, and drain form a first transistor, the semiconductor device further comprising:
a second transistor formed on the substrate, wherein the second transistor comprises a gate, dielectric, channel, source, and drain comprised of compounded layers of hafnium dioxide and zinc oxide.

8. The semiconductor device of claim 7 , wherein the first and second transistors are coupled to each other to form an inverter.

9. A method for producing a semiconductor device, the method comprising:
forming a gate on a substrate;
forming a dielectric on the gate;
forming a channel on the dielectric; and
forming a source and drain on the dielectric, wherein the source and drain are electrically coupled to the channel,
wherein each of the gate, dielectric, channel, source, and drain are formed of a corresponding mixture of hafnium dioxide (HfO 2 ) and zinc oxide (ZnO) layers and at least two of the gate, dielectric, channel, source, and drain are formed using different mixtures of the hafnium dioxide and zinc oxide layers.

10. The method of claim 9 , wherein each forming step is performed using atomic layer deposition (ALD) in a same reaction chamber.

11. The method of claim 9 , wherein each forming step involves forming at least one layer of one of hafnium dioxide and forming at least one layer of zinc oxide.

12. The method of claim 11 , wherein the dielectric, gate, source, and drain are formed by depositing a layer of zinc oxide on top of a plurality of layers of hafnium dioxide.

13. The method of claim 12 , wherein the dielectric includes fewer layers of hafnium dioxide than the gate, source, and drain.

14. The method of claim 11 , wherein the channel is formed by depositing a plurality of layers of hafnium dioxide on top of a plurality of layers of zinc oxide.

15. The method of claim 11 , wherein the hafnium dioxide is formed from a tetrakis (dimethylamido) hafnium (IV) precursor and the zinc oxide is formed from a diethyl zinc precursor.

16. An electronic device, comprising:
a first electrical compounded layer comprising a first set of layers of hafnium dioxide (HfO 2 ) and zinc oxide (ZnO) layers; and
a second electrical compounded layer coupled to the first electrical compounded layer and comprising a second set of layers of hafnium dioxide and zinc oxide,
wherein a number of layers of hafnium oxide and zinc oxide is different for the first and second set of layers.

17. The electronic device of claim 16 , further comprising:
a third electrical compounded layer coupled to the first electrical compounded layer, wherein the first electrical compounded layer is a dielectric layer arranged between the second and third electrical compounded layers and the electronic device is a capacitor.

18. The electronic device of claim 16 , wherein the first and second electrical compounded layers are semiconductor layers and the electronic device is a diode.

19. The electronic device of claim 16 , wherein the first electrical compounded layer is a gate layer and the second electrical compounded layer is a dielectric layer arranged on top of the gate layer, the electronic device further comprising:
a channel layer comprising a third set of layers of hafnium oxide and zinc oxide and arranged on top of the dielectric layer;
source and drain layers comprising a fourth set of layers of hafnium oxide and zinc oxide and arranged on top of the channel layer.

20. The electronic device of claim 16 , wherein the first electrical compounded layer comprises source and drain layers and the second electrical compounded layer is a channel layer arranged between the source and drain layers, the electronic device further comprising:
a dielectric layer comprising a third set of layers of hafnium oxide and zinc oxide and arranged on top of the source, drain, and channel layers;
a gate layer comprising a fourth set of layers of hafnium oxide and zinc oxide and arranged on top of the dielectric layer.

Assignees

• Univ King Abdullah Sci & Tech

Inventors

• Alshammari Fwzah Hamud
• Alshareef Husam Niman

Classifications

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title