Die edge integrity monitoring system

Patent metadata

Field	Value
Publication number	US-10964611-B2
Application number	US-201715819260-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Nov 24, 2016
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

An edge crack monitoring system for an integrated circuit provided on a die, comprises a conductive trace comprising at least a first conductive path for allowing current in a first direction, and a second adjacent conductive path for allowing current in a second direction opposite to the first direction. Both adjacent conductive paths form at least one loop surrounding a semiconductor device on a die. The arrangement of the trace is adapted to provide compensation of EM interferences. The trace comprises two terminals being connectable to a detection circuit for detecting damages by generating a fault signal upon detection of disruption of the conductive trace due to a damage. The conductive trace comprises high resistance portions with a resistance of at least 1 kΩ, adapted for reducing self-resonance.

First claim

The invention claimed is:

1. An edge crack monitoring system for an integrated circuit provided on a die, the system comprising a conductive trace comprising at least a first conductive path configured for allowing a low-intensity current in a first direction, and a second adjacent conductive path configured for allowing a low-intensity current in a second direction opposite to the first direction, both adjacent conductive paths forming at least one loop surrounding a semiconductor device on a die, wherein each of the at least one loops surround the semiconductor device along edges of the die, the arrangement of the trace being adapted to provide compensation of EM interferences, the trace comprising two terminals being connectable to a detection circuit for detecting damages by generating a fault signal upon detection of disruption of the conductive trace due to a damage,
wherein the conductive trace further comprises high resistance portions with a resistance of at least 1 kΩ adapted for reducing self-resonance, and the conductive trace further comprises polysilicon.

2. The monitoring system according to claim 1 , wherein the conductive trace is a bifilar trace.

3. The monitoring system according to claim 2 , wherein the conductive trace comprises a multi-layered stack of conductive paths.

4. The monitoring system according to claim 2 , wherein the conductive trace comprises at least one coplanar loop parallel with a die surface.

5. The monitoring system according to claim 2 , further comprising at least a further loop surrounding a semiconductor device, wherein the conductive trace comprises at least a coplanar loop parallel with a die surface and at least a multi-layered stack of conductive paths.

6. The monitoring system according to claim 1 , wherein the conductive trace comprises a multi-layered stack of conductive paths.

7. The monitoring system according to claim 1 , wherein the conductive trace comprises at least one coplanar loop parallel with a die surface.

8. The monitoring system according to claim 1 , further comprising at least a further loop surrounding a semiconductor device, wherein the conductive trace comprises at least a coplanar loop parallel with a die surface and at least a multi-layered stack of conductive paths.

9. The monitoring system according to claim 1 , further comprising a current source for providing a bias current to the at least one loop of conductive material.

10. The monitoring system according to claim 1 , further comprising an even number of conductive paths, each surrounding the die edge, each connected to adjacent conductive paths through connecting portions, the interconnected conductive paths thus forming a single conductive trace.

11. The monitoring system according to claim 1 , further comprising the detection circuit connected to the two terminals of the trace, wherein the detection circuit comprises a comparator connected to a debouncing unit.

12. The monitoring system according to claim 11 , wherein the detection circuit is adapted to detect damages and to generate a signal upon damage detection during at least the lifetime of the integrated circuit.

13. An integrated circuit comprising at least one die edge monitoring system according to claim 1 .

14. The integrated circuit according to claim 13 , further comprising an integrated detection circuit connected to the conductive trace.

Assignees

• Melexis Technologies Nv

Inventors

• Munder Gunnar
• Grimm Heiko
• Freitag Thomas

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title