Passivator for gate dielectric

Patent metadata

Field	Value
Publication number	US-10964543-B2
Application number	US-201916673555-A
Country	US
Kind code	B2
Filing date	Nov 4, 2019
Priority date	Jun 12, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin extending from a substrate; and
a gate dielectric layer over the fin;
deuterium located within the gate dielectric layer, the deuterium having a peak concentration in a range from 1 atomic percentage to 15 atomic percentage and a gradient concentration of the deuterium decreasing from the peak concentration;
a barrier layer in physical contact with the gate dielectric layer; and
a first work-function tuning layer in physical contact with the barrier layer.

2. The semiconductor device of claim 1 , further comprising an interfacial layer between the fin and the gate dielectric layer.

3. The semiconductor device of claim 2 , wherein the gradient concentration of the deuterium extends into the interfacial layer.

4. The semiconductor device of claim 3 , wherein the gradient concentration forms a first region with a first thickness, wherein the interfacial layer has a second thickness, and a ratio of the first thickness to the second thickness is from about 1:10 to about 1:60.

5. The semiconductor device of claim 4 , wherein the ratio is from about 1:20 to about 1:40.

6. The semiconductor device of claim 1 , further comprising deuterium located within the barrier layer.

7. The semiconductor device of claim 1 , further comprising a second work function tuning layer over the first work-function tuning layer.

8. A semiconductor device comprising:
an interlayer dielectric overlying a semiconductor fin;
a gate electrode embedded within the interlayer dielectric and over the semiconductor fin; and
a gate dielectric located between the gate electrode and the semiconductor fin, the gate dielectric having a changing concentration of deuterium with a peak concentration of between 1 atomic percentage to 15 atomic percentage.

9. The semiconductor device of claim 8 , further comprising an interfacial layer located between the semiconductor fin and the gate dielectric.

10. The semiconductor device of claim 9 , wherein the interfacial layer has a changing concentration of deuterium.

11. The semiconductor device of claim 10 , wherein the changing concentration of deuterium forms a first region with a first thickness, wherein the interfacial layer has a second thickness, and a ratio of the first thickness to the second thickness is from about 1:10 to about 1:60.

12. The semiconductor device of claim 8 , wherein the gate electrode further comprises a barrier layer, wherein the barrier layer has a changing concentration of deuterium.

13. The semiconductor device of claim 12 , wherein the gate electrode further comprises a work function tuning layer over the barrier layer.

14. The semiconductor device of claim 13 , wherein the gate electrode further comprises a fill material over the work function tuning layer.

15. A method of manufacturing a semiconductor device, the method comprising:
depositing a gate dielectric over a semiconductor fin;
cycling a first precursor and a second precursor over the semiconductor fin to deposit a dummy layer, wherein at least one of the first precursor and the second precursor comprise deuterium;
applying heat to the dummy layer, wherein the applying the heat drives the deuterium into the gate dielectric;
removing the dummy layer; and
forming a gate electrode over the gate dielectric.

16. The method of claim 15 , wherein the first precursor comprises silane.

17. The method of claim 15 , wherein the second precursor comprises deuterated silane.

18. The method of claim 15 , wherein the cycling the first precursor and the second precursor is performed in a first chamber and the applying the heat to the dummy layer is performed in the first chamber.

19. The method of claim 15 , wherein after the applying heat to the dummy layer, the gate dielectric has a peak concentration of deuterium of between 1 atomic percentage to 15 atomic percentage.

20. The method of claim 15 , wherein the dummy layer is conformal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tsung-Da
• Chang Che-Hao
• Hou Cheng-Hao
• Yu xiong-fei

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01354 Primary

  passivation or protection of the electrode, e.g. using re-oxidation · CPC title

• H10D64/0134 Primary

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10P14/42 Primary

  using a gas or vapour · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title