Magnetic memory, recording method of magnetic memory, and reading method of magnetic memory

Patent metadata

Field	Value
Publication number	US-10964366-B2
Application number	US-201816490142-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Mar 9, 2017
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

There is provided a magnetic memory that can suppress the increase in manufacturing costs while recording multivalued information in one memory cell, the memory including first and second tunnel junction elements each having a laminated structure including a reference layer with a fixed magnetization direction, a recording layer with a reversible magnetization direction, and an insulating layer sandwiched between the reference layer and the recording layer, a first selection transistor electrically connected to first ends of the first and second tunnel junction elements, a first wire electrically connected to a second end of the first tunnel junction element, and a second wire electrically connected to a second end of the second tunnel junction element.

First claim

The invention claimed is:

1. A magnetic memory, comprising:
a first tunnel junction element and a second tunnel junction element, wherein each of the first tunnel junction element and the second tunnel junction element has a laminated structure including:
a reference layer with a fixed magnetization direction;
a recording layer with a reversible magnetization direction; and
an insulating layer sandwiched between the reference layer and the recording layer;

a first selection transistor, wherein
a first terminal of the first selection transistor is electrically connected to a first end of the first tunnel junction element and a first end of the second tunnel junction element, and
a second terminal of the first selection transistor is electrically connected to a current-voltage conversion amplifier;

a first wire electrically connected to a second end of the first tunnel junction element; and
a second wire electrically connected to a second end of the second tunnel junction element.

2. The magnetic memory according to claim 1 , wherein the first tunnel junction element and the second tunnel junction element have magnetic characteristics substantially identical to each other.

3. The magnetic memory according to claim 2 , wherein
the first tunnel junction element and the second tunnel junction element have shapes substantially identical to each other,
each layer of the first tunnel junction element and the second tunnel junction element has a common material, and
each layer of the first tunnel junction element and the second tunnel junction element has a substantially identical film thickness.

4. The magnetic memory according to claim 1 , further comprising:
a third tunnel junction element having the laminated structure; and
a second selection transistor electrically connected to a first end of the third tunnel junction element, wherein a second end of the third tunnel junction element is electrically connected to the second wire.

5. A magnetic memory, comprising:
a plurality of memory cells arranged in a matrix, wherein each of the plurality of memory cells includes:
a plurality of tunnel junction elements, each of the plurality of tunnel junction elements having a laminated structure including:
a reference layer with a fixed magnetization direction;
a recording layer with a reversible magnetization direction; and
an insulating layer sandwiched between the reference layer and the recording layer;

a selection transistor, wherein
a first terminal of the selection transistor is electrically connected to a plurality of first ends of the plurality of tunnel junction elements, and
a second terminal of the selection transistor is electrically connected to a current-voltage conversion amplifier; and

a plurality of wires electrically connected to a second end of each of the plurality of tunnel junction elements.

6. The magnetic memory according to claim 5 , wherein two memory cells, of the plurality of memory cells, adjacent to each other share at least one of the plurality of wires.

7. The magnetic memory according to claim 6 , wherein, in the two memory cells of the plurality of memory cells adjacent to each other, selection transistors share one of a source or a drain with each other.

8. A recording method of a magnetic memory,
the magnetic memory comprising:
a first tunnel junction element and a second tunnel junction element, wherein each of the first tunnel junction element and the second tunnel junction element has a laminated structure including:
a reference layer with a fixed magnetization direction;
a recording layer with a reversible magnetization direction; and
an insulating layer sandwiched between the reference layer and the recording layer;

a selection transistor, wherein
a terminal of the selection transistor is electrically connected to a first end of the first tunnel junction element and a first end of the second tunnel junction element;

a first wire electrically connected to a second end of the first tunnel junction element; and
a second wire electrically connected to a second end of the second tunnel junction element,

the recording method comprising:
bringing the selection transistor into a conductive state; and
providing a potential difference between the first wire and the second wire.

9. A recording method of a magnetic memory,
the magnetic memory comprising:
a plurality of memory cells arranged in a matrix, wherein each of the plurality of memory cells includes:
a plurality of tunnel junction elements, each of the plurality of tunnel junction elements having a laminated structure including:
a reference layer with a fixed magnetization direction;
a recording layer with a reversible magnetization direction; and
an insulating layer sandwiched between the reference layer and the recording layer;

a selection transistor, wherein
a terminal of the selection transistor is electrically connected to a plurality of first ends of the plurality of tunnel junction elements; and

a plurality of wires electrically connected to a second end of each of the plurality of tunnel junction elements,

the recording method comprising:
in the plurality of memory cells:
bringing the selection transistor into a conductive state; and
providing a potential difference between the plurality of wires.

10. The recording method of the magnetic memory according to claim 9 , further comprising, in the plurality of memory cells:
bringing a plurality of selection transistors into the conductive state;
sequentially switching a voltage applied to each of the plurality of wires from a first voltage to a second voltage; and
subsequent to the sequential switch of the voltage from the first voltage to the second voltage, sequentially switching the voltage applied to each of the plurality of wires from the second voltage to the first voltage.

11. A reading method of a magnetic memory,
the magnetic memory comprising:
a first tunnel junction element and a second tunnel junction element, wherein each of the first tunnel junction element and the second tunnel junction element has a laminated structure including:
a reference layer with a fixed magnetization direction;
a recording layer with a reversible magnetization direction; and
an insulating layer sandwiched between the reference layer and the recording layer;

a selection transistor, wherein
a first terminal of the selection transistor is electrically connected to

a first end of the first tunnel junction element and a first end of the second tunnel junction element;
a first wire electrically connected to a second end of the first tunnel junction element;
a second wire electrically connected to a second end of the second tunnel junction element; and
a third wire electrically connected to a second terminal of the selection transistor,

the reading method comprising:
bringing the selection transistor into a conductive state;
applying a first voltage to the first wire and the second wire such that the first wire and second wire have a first polarity with respect to the third wire; and
applying, subsequent to the application of the first voltage, a second voltage to one of the first wire or the second wire such that one of the first wire or the second wire has a second polarity, opposite to the first polarity, with respect to the third wire.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Ohmori Hiroyuki
• Hosomi Masanori
• Higo Yutaka
• Uchida Hiroyuki
• Hase Naoki
• Sato Yo

Classifications

• H10D48/40

  Devices controlled by magnetic fields · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659

  Cell access · CPC title