Scan driving circuit, driving method, and display device

Patent metadata

Field	Value
Publication number	US-10964268-B2
Application number	US-201816202528-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	May 9, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

The present disclosure provides a shift register, a driving method thereof, a scan driving circuit and a display device. The shift register includes: a first node control module configured to control level at the first node based on an input signal and a second clock signal; a second node control module configured to control level at a second node based on the input signal, the first clock signal, the second clock signal, a low level signal and a high level signal; and an output control module configured to control the output terminal to output high level or low level based on level at the first node, level at the second node and the second clock signal. The second node can be provided with a relatively low level, which is conductive to maintaining a normal output of the shift register.

First claim

What is claimed is:

1. A scan driving circuit, comprising a plurality of cascaded shift registers, wherein at each stage of the plurality of cascaded shift registers, a shift register comprises:
a first node control module electrically connected to an input signal terminal, a second clock signal terminal and a first node, and configured to control a level at the first node based on an input signal and a second clock signal;
a second node control module electrically connected to the input signal terminal, a first clock signal terminal, the second clock signal terminal, a low level signal terminal, a high level signal terminal and a second node, and configured to control a level at the second node based on the input signal, a first clock signal, the second clock signal, a low level signal and a high level signal, wherein a level at a third node controls writing of the first clock signal into a fourth node, the first clock signal controls writing of a level at the fourth node into the second node, and pulls down the level at the third node when the level at the fourth node changes to a low level; a low level of the first clock signal is completely written into the fourth node to allow the level at the fourth node to be lower; the low level at the fourth node is written into the second node to allow the level at the second node to be lower; and
an output control module electrically connected to the first node, the second node, the high level signal terminal, the second clock signal terminal and an output terminal, and configured to control the output terminal to output a high level or a low level based on the level at the first node, the level at the second node and the second clock signal,
wherein the second node control module comprises:
a first transistor having a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the low level signal terminal, and a second terminal electrically connected to the third node;
a second transistor having a control terminal electrically connected to the third node, a first terminal electrically connected to the first clock signal terminal, and a second terminal electrically connected to the fourth node;
a third transistor having a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the fourth node, and a second terminal electrically connected to the second node; and
a first capacitor having a first terminal electrically connected to the third node and a second terminal electrically connected to the fourth node.

2. The scan driving circuit according to claim 1 , wherein the second node control module further comprises:
a fourth transistor having a control terminal electrically connected to the input signal terminal, a first terminal electrically connected to the third node, and a second terminal electrically connected to the fourth node;
a fifth transistor having a control terminal electrically connected to the input signal terminal, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the fourth node; and
a second capacitor having a first terminal electrically connected to the high level signal terminal and a second terminal electrically connected to the second node.

3. The scan driving circuit according to claim 1 , wherein the first node control module is also electrically connected to the first clock signal terminal, and the first node control module is further configured to control writing of the input signal into a fifth node based on the first clock signal and to control writing of a level at the fifth node into the first node based on the first clock signal.

4. The scan driving circuit according to claim 3 , wherein the first node control module comprises:
a sixth transistor having a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal, and a second terminal electrically connected to the fifth node; and
a seventh transistor having a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the fifth node, and a second terminal electrically connected to the first node.

5. The scan driving circuit according to claim 3 , wherein the first node control module further comprises a third capacitor, and the a third capacitor has a first terminal electrically connected to the output terminal and a second terminal electrically connected to the first node.

6. The scan driving circuit according to claim 1 , wherein the first node control module is further electrically connected to the first clock signal terminal, and the first node control module is further configured to control writing of the input signal into a fifth node based on the first clock signal and to control writing of a level at the fifth node into the first node based on the first clock signal and the second clock signal.

7. The scan driving circuit according to claim 6 , wherein the first node control module comprises:
a sixth transistor having a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal, and a second terminal electrically connected to the fifth node;
a seventh transistor having a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the fifth node, and a second terminal electrically connected to the first node; and
an eighth transistor having a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the fifth node, and a second terminal electrically connected to the first node.

8. The scan driving circuit according to claim 6 , wherein the first node control module further comprises a third capacitor, and the a third capacitor has a first terminal electrically connected to the output terminal and a second terminal electrically connected to the first node.

9. The scan driving circuit according to claim 1 , wherein the first node control module is further electrically connected to the low level signal terminal, the second node and the high level signal terminal, and the first node control module is further configured to control writing of the low level signal into the first node based on the input signal and to control writing of the high level signal into the first node based on the level at the second node.

10. The scan driving circuit according to claim 9 , wherein the first node control module comprises:
a ninth transistor having a control terminal electrically connected to the input signal terminal, a first terminal electrically connected to the low level signal terminal, and a second terminal electrically connected to the first node; and
a tenth transistor having a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal terminal, and a second terminal electrically connected to the first node.

11. The scan driving circuit according to claim 9 , wherein the first node control module further comprises a third capacitor, and the a third capacitor has a first terminal electrically connected to the output terminal and a second terminal electrically connected to the first node.

12. The scan driving circuit according to claim 1 , wherein the output control module comprises:
an eleventh transistor having a control terminal electrically connected to the second node, a first terminal electrically connected to the high level signal termina

Assignees

• Shanghai Tianma Am Oled Co Ltd

Inventors

• Zhu Renyuan
• Li Yue
• Xiang Dongxu
• Gao Yana
• Zhou Xingyao

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title