Shift register circuit and its driving method, gate driving circuit and its driving method, and display device

Patent metadata

Field	Value
Publication number	US-10964243-B2
Application number	US-201916515880-A
Country	US
Kind code	B2
Filing date	Jul 18, 2019
Priority date	Jan 4, 2019
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A shift register circuit according to an embodiment of the present disclosure includes an input sub-circuit and N-stage output sub-circuits. The input sub-circuit is configured to transmit an input signal to a pull up node at a first stage. The output sub-circuit at each stage is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of a pull-up node at the same stage. The output sub-circuit at each stage is further configured to transmit a signal transmitted to an output signal terminal at the same stage to a pull-up node at an immediately subsequent stage under the control of a shift control signal from a shift control signal terminal at the same stage.

First claim

What is claimed is:

1. A shift register circuit, comprising:
an input sub-circuit, electrically coupled to an input signal terminal and a pull-up node at a first stage, and configured to transmit an input signal from the input signal terminal to the pull-up node at the first stage;
output sub-circuits at first to N th stages, of which an output sub-circuit at each stage is electrically coupled to a clock signal terminal at a corresponding stage of clock signal terminals at first to N th stages, to a pull-up node at a corresponding stage of pull-up nodes at the first to N th stages, to an output signal terminal at a corresponding stage of output signal terminals at first to N th stages, and to a shift control signal terminal at a corresponding stage of shift control signal terminals at first to N th stages, an output sub-circuit at each stage of the output sub-circuits at the first to (N−1) th stages being electrically coupled to a pull-up node at an immediately subsequent stage, where N is an integer greater than 1,
wherein an output sub-circuit at each stage of the output sub-circuits at the first to N th stages is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of the pull-up node at the same stage, and
the output sub-circuit at each stage of the output sub-circuits at the first to (N−1) th stages is further configured to, under a shift control signal from a shift control signal terminal at the same stage, transmit a signal from the output signal terminal at the same stage to a pull-up node at an immediately subsequent stage.

2. The shift register circuit according to claim 1 , further comprising:
pull-down sub-circuits at first to N th stages, electrically coupled in a one-to-one correspondence to the output sub-circuits at the first to N th stages;
wherein a pull-down sub-circuit at each stage of the pull-down sub-circuits at the first to N th stages is electrically coupled to a pull-down node, a first constant voltage signal terminal and an output signal terminal at a same stage, and configured to transmit a signal from the first constant voltage signal terminal to a signal output terminal at the same stage and an output sub-circuit at the same stage under the control of the pull-down node.

3. The shift register circuit according to claim 2 , further comprising:
a control sub-circuit, electrically coupled to the first constant voltage signal terminal, a second constant voltage signal terminal, the pull-up node at the first stage, and the pull-down node,
wherein the control sub-circuit is configured to transmit a signal from the first constant voltage signal terminal or from the second constant voltage signal terminal to the pull-down node under the control of the pull-up node at the first stage.

4. The shift register circuit according to claim 3 , further comprising:
a reset sub-circuit, electrically coupled to a reset signal terminal, the first constant voltage signal terminal, and the pull-up node at the first stage,
wherein the reset sub-circuit is configured to transmit, under the control of a signal from the reset signal terminal, a signal from the first constant voltage signal terminal to the pull-up node at the first stage to reset the pull-up node at the first stage.

5. The shift register circuit according to claim 1 , wherein an output sub-circuit at each stage comprises an output transistor, a shift transistor, and a storage capacitor,
wherein a control electrode of the output transistor is electrically coupled to a pull-up node at a same stage, a first electrode of the output transistor is electrically coupled to a clock signal terminal at the same stage, and a second electrode of the output transistor is electrically coupled to an output signal terminal at the same stage;
wherein a control electrode of the shift transistor is electrically coupled to a shift control signal terminal at the same stage, a first electrode of the shift transistor is electrically coupled to an output signal terminal at the same stage, and a second electrode of the shift transistor is electrically coupled to a pull-up node at an immediately subsequent stage; and
wherein a first electrode of the storage capacitor is electrically coupled to a pull-up node at the same stage, and a second electrode of the storage capacitor is electrically coupled to a shift output signal terminal at the same stage.

6. The shift register circuit according to claim 2 , wherein a pull-down sub-circuit at each stage comprises a pull-down transistor and a shift pull-down transistor,
wherein a control electrode of the pull-down transistor is electrically coupled to the pull-down node, a first electrode of the pull-down transistor is electrically coupled to the first constant voltage signal terminal, and a second electrode of the pull-down transistor is electrically coupled to an output signal terminal at a same stage; and
wherein a control electrode of the shift pull-down transistor is electrically coupled to the pull-down node, a first electrode of the shift pull-down transistor is electrically coupled to the first constant voltage signal terminal, and a second electrode of the shift pull-down transistor is electrically coupled to an output sub-circuit at the same stage.

7. The shift register circuit according to claim 1 , wherein the input sub-circuit comprises a first transistor, wherein a control electrode and a first electrode of the first transistor is electrically coupled to the input signal terminal, and a second electrode of the first transistor is electrically coupled to the pull-up node at the first stage.

8. The shift register circuit according to claim 3 , wherein the control sub-circuit comprises a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein a control electrode and a first electrode of the second transistor are electrically coupled to the second constant voltage signal terminal, and a second electrode of the second transistor is electrically coupled to a control electrode of the third transistor;
wherein a first electrode of the third transistor is electrically coupled to the second constant voltage signal terminal, and a second electrode of the third transistor is electrically coupled to the pull-down node;
wherein a control electrode of the fourth transistor is electrically coupled to the pull-up node at the first stage, a first electrode of the fourth transistor is electrically coupled to the first constant voltage signal terminal, and a second electrode of the fourth transistor is electrically coupled to the control electrode of the third transistor; and
wherein a control electrode of the fifth transistor is electrically coupled to the pull-up node at the first stage, a first electrode of the fifth transistor is electrically coupled to the first constant voltage signal terminal, and a second electrode of the fifth transistor is electrically coupled to the pull down node.

9. The shift register circuit according to claim 8 , wherein the control sub-circuit further comprises a sixth transistor, wherein
a control electrode of the sixth transistor is electrically coupled to the pull-down node, a first electrode of the sixth transistor is electrically coupled to the first constant voltage signal terminal, and a second electrode of the sixth transistor is electrically coupled to the pull-up node at the first stage.

10. The shift register circuit according to claim 4 , wherein the reset sub-circuit comprises a seventh transistor, wherein
a control electrode of the seventh transistor is electrically coupled to the reset signal terminal, a first electrode of the seventh t

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yuan Lijun
• Yao Xing
• Shang Guangliang
• Zheng Haoliang
• Zhang Zhenyu

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title