Hardware assisted remote transactional memory

Patent metadata

Field	Value
Publication number	US-10963383-B2
Application number	US-201815979511-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	May 15, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

Hardware assisted remote transactional memory including receiving, from a first remote processor over a high-speed communications fabric, an indication of a beginning of a first memory transaction; queuing, in a first hardware memory assistant, memory instructions for the first memory transaction; receiving, from a second remote processor over the high-speed communications fabric, an indication of a beginning of a second memory transaction; queuing, in a second hardware memory assistant, memory instructions for the second memory transaction; receiving, from the first remote processor over the high-speed communications fabric, an indication of an ending of the first memory transaction; comparing memory addresses accessed in the first memory transaction to memory addresses accessed in the second memory transaction; and in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the first memory transaction.

First claim

What is claimed is:

1. A method comprising:
by program instructions on a computing device,
receiving, by a first hardware memory assistant within a shared memory system, from a first remote processor over a high-speed communications fabric, an indication of a beginning of a first memory transaction, wherein the shared memory system is remote from the first remote processor and a second remote processor;
queuing, in a first queue of the first hardware memory assistant, memory instructions for the first memory transaction received from the first remote processor over the high-speed communications fabric;
receiving, by a second hardware memory assistant within the shared memory system, from the second remote processor over the high-speed communications fabric, an indication of a beginning of a second memory transaction;
queuing, in a second queue of the second hardware memory assistant, memory instructions for the second memory transaction received from the second remote processor over the high-speed communications fabric;
receiving, from the first remote processor over the high-speed communications fabric, an indication of an ending of the first memory transaction;
comparing memory addresses accessed in the first memory transaction to memory addresses accessed in the second memory transaction; and
in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the first memory transaction.

2. The method of claim 1 , further comprising:
in response to determining that the memory addresses accessed in the first memory instructions do not overlap with the memory addresses accessed in the second memory instructions:
committing the first memory transaction to shared memory; and
sending, to the first remote processor, a confirmation that the first memory transaction has been committed to memory.

3. The method of claim 2 , wherein comparing the memory addresses accessed in the first memory transaction to the memory addresses accessed in the second memory transaction comprises locking the second hardware memory assistant; and
in response to determining that the memory addresses accessed in the first memory instructions do not overlap with the memory addresses accessed in the second memory instructions, unlocking the second hardware memory assistant.

4. The method of claim 1 , further comprising: in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the second memory transaction.

5. The method of claim 1 , wherein comparing the memory addresses accessed in the first memory transaction to the memory addresses accessed in the second memory transaction comprises comparing the memory address from the memory instructions queued in the first hardware memory assistant to the memory addresses from the memory instructions queued in the second hardware memory assistant.

6. The method of claim 1 , wherein the first hardware memory assistant and the second hardware memory assistant are each a collection of hardware logic and reside on a hardware memory assistant switch communicatively coupled to remote shared memory targeted by the first memory transaction and the second memory transaction, wherein both the hardware memory assistant switch and the remote shared memory are within the shared memory system that is remote from the first and second remote processors.

7. The method of claim 1 , wherein the first hardware memory assistant is assigned to the first remote processor, and wherein the second hardware memory assistant is assigned to the second remote processor.

8. An apparatus comprising a computing device, a computer processor, and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
receiving, by a first hardware memory assistant within a shared memory system, from a first remote processor over a high-speed communications fabric, an indication of a beginning of a first memory transaction, wherein the shared memory system is remote from the first remote processor and a second remote processor;
queuing, in a first queue of the first hardware memory assistant, memory instructions for the first memory transaction received from the first remote processor over the high-speed communications fabric;
receiving, by a second hardware memory assistant within the shared memory system, from the second remote processor over the high-speed communications fabric, an indication of a beginning of a second memory transaction;
queuing, in a second queue of the second hardware memory assistant, memory instructions for the second memory transaction received from the second remote processor over the high-speed communications fabric;
receiving, from the first remote processor over the high-speed communications fabric, an indication of an ending of the first memory transaction;
comparing memory addresses accessed in the first memory transaction to memory addresses accessed in the second memory transaction; and
in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the first memory transaction.

9. The apparatus of claim 8 , wherein the computer program instructions further cause the apparatus to carry out the steps of:
in response to determining that the memory addresses accessed in the first memory instructions do not overlap with the memory addresses accessed in the second memory instructions:
committing the first memory transaction to shared memory; and
sending, to the first remote processor, a confirmation that the first memory transaction has been committed to memory.

10. The apparatus of claim 9 , wherein comparing the memory addresses accessed in the first memory transaction to the memory addresses accessed in the second memory transaction comprises locking the second hardware memory assistant; and
in response to determining that the memory addresses accessed in the first memory instructions do not overlap with the memory addresses accessed in the second memory instructions, unlocking the second hardware memory assistant.

11. The apparatus of claim 8 , wherein the computer program instructions further cause the apparatus to carry out the steps of:
in response to determining that the memory addresses accessed in the first memory transaction overlap with the memory addresses accessed in the second memory transaction, aborting the second memory transaction.

12. The apparatus of claim 8 , wherein comparing the memory addresses accessed in the first memory transaction to the memory addresses accessed in the second memory transaction comprises comparing the memory address from the memory instructions queued in the first hardware memory assistant to the memory addresses from the memory instructions queued in the second hardware memory assistant.

13. The apparatus of claim 8 , wherein the first hardware memory assistant and the second hardware memory assistant are each a collection of hardware logic and reside on a hardware memory assistant switch communicatively coupled to remote shared memory targeted by the first memory transaction and the second memory transaction, wherein both the hardware memory assistant switch and the remote shared memory are within the shared memory system that is remote from the first and second remote processo

Assignees

• Lenovo Entpr Solutions Singapore Pte Ltd

Inventors

• Ono Makoto

Classifications

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F2212/656

  Address space sharing · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title