Synchronization and exchange of data between processors

Patent metadata

Field	Value
Publication number	US-10963315-B2
Application number	US-201916276834-A
Country	US
Kind code	B2
Filing date	Feb 15, 2019
Priority date	Jul 4, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A system comprising: a first subsystem comprising one or more first processors, and a second subsystem comprising one or more second processors. The second subsystem is configured to process code over a series of steps delineated by barrier synchronizations, and in a current step, to send a descriptor to the first subsystem specifying a value of each of one or more parameters of each of one or more interactions that the second subsystem is programmed to perform with the first subsystem via an inter-processor interconnect in a subsequent step. The first subsystem is configured to execute a portion of code to perform one or more preparatory operations, based on the specified values of at least one of the one or more parameters of each interaction as specified by the descriptor, to prepare for said one or more interactions prior to the barrier synchronization leading into the subsequent phase.

First claim

What is claimed is:

1. A processing system comprising:
a first subsystem comprising one or more first processors, and
a second subsystem comprising one or more second processors;
wherein the second subsystem is configured to process code over a series of steps, each next step in the series being delineated from its preceding step by a barrier synchronization whereby the second subsystem waits to advance to the next step until the second subsystem receives a synchronization acknowledgement signal indicating that the advancement is agreed by the first subsystem;
wherein the second subsystem is configured, in a current one of said steps, to send a descriptor to the first subsystem specifying a value of each of one or more parameters of each of one or more interactions that the second subsystem is programmed to perform with the first subsystem via an inter-processor interconnect in a subsequent one of said steps; and
wherein the first subsystem is configured to execute a portion of code to perform one or more preparatory operations, based on the specified values of at least one of the one or more parameters of each interaction as specified by the descriptor, to prepare for said one or more interactions prior to the barrier synchronization leading into said subsequent step.

2. The processing system of claim 1 , wherein:
the first subsystem stores one or more look-up tables mapping each of a set of behaviour IDs to a different respective one of a plurality of different possible predetermined definitions for said interaction, each definition comprising a respective set of values for said one or more parameters;
the descriptor specifies the specified values of the one or more parameters of each interaction by indicating one of the behaviour IDs; and
the first subsystem is configured to determine the specified values by looking up the definition mapped to the indicated behaviour ID in said one or more look-up tables, and to perform said one or more preparatory operations based on the respective set of values of the looked-up definition.

3. The processing system of claim 1 , wherein at least one of the one or more interactions is to transfer data between the second subsystem and a memory of the first subsystem, and wherein the one or more preparatory operations comprise one or more operations to prepare the memory for the transfer.

4. The processing system of claim 3 , wherein the at least one parameter comprises a direction of the transfer, the direction being either: incoming from the second subsystem to the memory of the first subsystem, or outgoing from the memory of the first subsystem to the second subsystem.

5. The processing system of claim 3 , wherein the transfer comprises transferring an incoming portion of data from the second subsystem to the memory of the first subsystem, wherein said at least one parameter comprises at least a size of the incoming portion of data, and wherein said one or more preparatory operations comprise at least: reserving a corresponding amount of space in the memory ready to accept the incoming portion of data from the second subsystem in the subsequent step.

6. The processing system of claim 1 , wherein the transfer comprises transferring an outgoing portion of data to the second subsystem from the memory of the first subsystem, wherein said at least one parameter comprises at least a size of the outgoing portion of data, and wherein said one or more preparatory operations comprise one, more or all of: reserving a corresponding amount space in the memory to store the outgoing portion of data, generating the outgoing portion of data, and storing the outgoing portion of data in the memory ready to send to the second subsystem in the subsequent step.

7. The processing system of claim 5 , wherein the memory comprises a first-in, first-out (FIFO) buffer and the reserved space is space in the FIFO.

8. The processing system of claim 3 , wherein at least one of said one or more interactions is to transfer the data as part of a stream; and wherein the one or more parameters for each stream comprise at least a stream ID identifying a stream, an indication that the second subsystem is to begin streaming between the second subsystem and the memory of the first subsystem in the subsequent step, and a direction of the stream.

9. The processing system of claim 2 , wherein:
at least one of the one or more interactions is to transfer data between the second subsystem and a memory of the first subsystem, and wherein the one or more preparatory operations comprise one or more operations to prepare the memory for the transfer;
the at least one parameter comprises a direction of the transfer, the direction being either: incoming from the second subsystem to the memory of the first subsystem, or outgoing from the memory of the first subsystem to the second subsystem;
at least one of said one or more interactions is to transfer the data as part of a stream, wherein the one or more parameters for each stream comprise at least a stream ID identifying a stream, an indication that the second subsystem is to begin streaming between the second subsystem and the memory of the first subsystem in the subsequent step, and a direction of the stream; and
the stream ID is mapped to the behaviour ID in a first of said look-up tables, and wherein the portion size and direction are mapped to the stream ID in a second of said look-up tables.

10. The processing system of claim 1 , wherein said subsequent step is the next step following the current step in said series by default.

11. The processing system of claim 1 , wherein said subsequent step is operable to be any of a number of steps following the current step in said series, wherein said number is specified by the descriptor.

12. The processing system of claim 1 , wherein the descriptor specifies at least one interaction for each of the next N steps following the current step in said series, where N is specified by the descriptor; the first subsystem being configured to prepare for each of said N steps prior to the respective barrier leading into each.

13. The processing system of claim 1 , comprising synchronization logic configured to return the synchronization acknowledgement signal to the second subsystem on condition of: i) receiving a synchronization request signal from the second subsystem, and ii) receiving permission from the first subsystem system to return the synchronization acknowledgement.

14. The processing system of claim 13 , wherein the synchronization logic comprises a register for storing a number of credits, the register being writeable by the first subsystem; wherein said permission is granted when the register is written with at least one credit but denied when the credits are exhausted; and wherein the synchronization logic is configured to automatically decrement the number of credits in the register each time an instance of the synchronization acknowledgement signal is returned to the second subsystem.

15. The processing system of claim 1 , wherein each of the one or more second processors comprises an array of tiles each comprising a respective execution unit and memory, the tiles being arranged to exchange data with one another by an inter-tile interconnect.

16. The processing system of claim 3 , wherein
each of the one or more second processors comprises an array of tiles each comprising a respective execution unit and memory, the tiles being arranged to exchange data with one another by an inter-tile interconnect; and
the inter-tile interconnect is a time-deterministic interconnect for exchanging data between the tiles in a

Assignees

• Graphcore Ltd

Inventors

• Lacey David
• Wilkinson Daniel John Pelham
• Osborne Richard Luke Southwell
• Fyles Matthew David

Classifications

• H04L49/10

  characterised by the switching fabric construction · CPC title

• H04L47/10

  Flow control; Congestion control · CPC title

• G06F9/522 Primary

  Barrier synchronisation · CPC title

• G06F13/4059 Primary

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title

• H04L47/39

  Credit based · CPC title