Single event latch-up (SEL) mitigation detect and mitigation

Patent metadata

Field	Value
Publication number	US-10958067-B2
Application number	US-201816136104-A
Country	US
Kind code	B2
Filing date	Sep 19, 2018
Priority date	Sep 19, 2018
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

First claim

What is claimed is:

1. An integrated circuit (IC) chip, comprising:
a body having a plurality of contact pads:
a power rail disposed in the body and coupled to at least one of the plurality of contact pads; and
a first core circuit disposed in the body, the first core circuit comprising:
a first current limiting circuit coupled to the power rail;
a silicon controlled rectifier (SCR) device including a first transistor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the first current limiting circuit;
a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the first current limiting circuit; and
a first latch sensing circuit having a first input terminal coupled to the second terminals of the first and second transistors, the first latch sensing circuit having an output terminal coupled to the first current limiting circuit.

2. The IC chip of claim 1 , wherein the first latch sensing circuit further comprises:
a comparator having a second input terminal configured to receive a reference voltage.

3. The IC chip of claim 2 , wherein the first core circuit further comprises:
a resistor having a first terminal coupled to the first input terminal of the comparator and a second terminal coupled to at least one of the plurality of contact pads that is configured to couple to ground.

4. The IC chip of claim 1 , wherein the first current limiting circuit further comprises:
a resistor and a first current limiting transistor coupled in series between the power rail and the first terminal of the first transistor; and
a second current limiting transistor coupled between the power rail and the first terminal of the first transistor, wherein one of the first and second current limiting transistors is an N-type transistor and the other of the first and second current limiting transistors is an P-type transistor.

5. The IC chip of claim 1 , wherein the first current limiting circuit further comprises:
a variable resistor and a first current limiting transistor coupled in series between the power rail and the first terminal of the first transistor; and
a second current limiting transistor coupled between the power rail and the first terminal of the first transistor, wherein one of the first and second current limiting transistors is an N-type transistor and the other of the first and second current limiting transistors is an P-type transistor.

6. The IC chip of claim 5 , wherein the variable resistor is configured increase in resistance in response to an increase in current at the first terminal of the first transistor.

7. The IC chip of claim 5 , wherein the first latch sensing circuit further comprises:
an amplifier having an input terminal coupled to the second terminal of the first transistor and an output terminal coupled to a control terminal of the variable resistor.

8. The IC chip of claim 1 , wherein:
the first current limiting circuit further comprises:
a current limiting transistor having a first terminal coupled to the power rail and a second terminal coupled to the first terminal of the first transistor; and

the first latch sensing circuit further comprises:
an amplifier having an output terminal coupled to a gate terminal of the current limiting transistor.

9. The IC chip of claim 8 , wherein the first latch sensing circuit further comprises:
a comparator coupled to the second terminals of the first and second transistors, a second input terminal configured to receive a reference voltage, and an output terminal coupled to a first contact pad of the plurality of contact pads.

10. The IC chip of claim 1 , wherein the first latch sensing circuit is configured to:
output a first signal in response to the SCR device operating in an unlatched state; and
output a second signal in response to the SCR device operating in a latched state.

11. The IC chip of claim 1 , wherein the first current limiting circuit is configured to:
reduce current passing from the power rail to the SCR device in response to a signal being received from the first latch sensing circuit switching from the first signal to the second signal.

12. The IC chip of claim 1 further comprising:
a second core circuit disposed in the body, the second core circuit comprising:
a second current limiting circuit coupled to the power rail;
a second silicon controlled rectifier (SCR) device including third transistor having a first terminal and a second terminal, the first terminal of the third transistor coupled to the second current limiting circuit;
a fourth transistor having a first terminal and a second terminal, the first terminal of the fourth transistor coupled to the second current limiting circuit; and
a second latch sensing circuit having a first input terminal coupled to the first terminals of the third and fourth transistors, the second latch sensing circuit having an output terminal coupled to the second current limiting circuit.

13. The IC chip of claim 1 , wherein:
the first current limiting circuit further comprises:
a current limiting transistor having a first terminal coupled to the power rail and a second terminal coupled to the first terminal of the first transistor; and

the first latch sensing circuit further comprises:
a comparator having a second input terminal configured to receive a reference voltage and an output terminal coupled to a gate terminal of the current limiting transistor.

14. An integrated circuit (IC) chip, comprising:
a body having a plurality of contact pads:
a power rail disposed in the body and coupled to at least one of the plurality of contact pads;
a silicon controlled rectifier (SCR) device having a first transistor disposed in the body, the first transistor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the power rail;
a second transistor disposed in the body and having a first terminal and a second terminal, the first terminal of the second transistor coupled to the power rail;
a first latch sensing circuit configured to output a first signal in response to the SCR device operating in an unlatched state, and to output a second signal in response to the SCR device operating in a latched state; and
a first current limiting circuit coupling the first and second transistors to the power rail, the first current limiting circuit configured to reduce current passing from the power rail to the SCR device in response to a signal being received from the first latch sensing circuit switching from the first signal to the second signal.

15. The IC chip of claim 14 , wherein the first current limiting circuit is further configured to:
when reducing current, increase a resistance between the power rail and the SCR device and the second transistor.

16. The IC chip of claim 15 , wherein the first current limiting circuit further comprises:
a variable resistor disposed between the power rail and the first and second transistors.

17. The IC chip of claim 15 , wherein the first current limiting circuit further comprises a transistor having a first terminal coupled to the power rail and a second terminal coupled to the first and second transistors; and
wherein the first latch sensing circuit further comprises an amplifier having an output terminal coupled to a gate terminal of the transistor of the current limiting circuit and an input terminal coupled to the second terminals of the first and second transistors.

18. The IC chip of claim 14 , w

Assignees

• Xilinx Inc

Inventors

• Maillard Pierre
• Chen Yanran
• Hart Michael J

Classifications

• H02H5/005 Primary

  responsive to ionising radiation; Nuclear-radiation circumvention circuits (radiation detectors G01T; nuclear-explosion detection G21J5/00) · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title