Methods and apparatus for maintaining characterized memory devices

Patent metadata

Field	Value
Publication number	US-10957416-B2
Application number	US-201916276489-A
Country	US
Kind code	B2
Filing date	Feb 14, 2019
Priority date	Feb 14, 2019
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach.

First claim

What is claimed is:

1. A computerized method for monitoring a performance of characterized memories, the computerized method comprising:
accessing contents of a characterized memory at a characterized rate with a processor, wherein the characterized memory has one or more uncorrectable faults, the characterized memory characterized by a target performance based at least on the one or more uncorrectable faults;
determining an actual performance with the processor; and
refreshing the contents of the characterized memory with the processor based at least on the actual performance exceeding the target performance by a bound amount.

2. The computerized method of claim 1 , wherein the refreshing the contents of the characterized memory comprises re-writing the contents of the characterized memory with a pristine copy of the contents.

3. The computerized method of claim 1 , wherein the determining the actual performance is based at least on monitoring an increase in uncorrectable faults attributed to probabilistic errors.

4. The computerized method of claim 1 , wherein the accessing the contents of the characterized memory comprises a plurality of uniformly distributed memory reads over a memory space.

5. The computerized method of claim 1 , wherein the determining the actual performance comprises calculating a bit error rate (BER) based at least on the accessed contents and a pristine copy of the contents.

6. The computerized method of claim 1 , further comprising re-characterizing the characterized memory with a new target performance based at least on the actual performance exceeding the target performance by the bound amount.

7. The computerized method of claim 1 , wherein the determining the actual performance comprises determining a rate of change of faults.

8. The computerized method of claim 1 , wherein the determining the actual performance comprises determining a total accumulated number of faults.

9. The computerized method of claim 1 , wherein the target performance is based on a solution density function for an error-tolerant application.

10. A computerized method for estimating a degradation of one or more characterized memories, the computerized method comprising:
accessing contents of a characterized memory at a characterized rate with a processor, the characterized memory characterized by a target performance which is less than another target performance associated with another prescribed memory in data communication with the characterized memory;
determining an actual performance of the characterized memory with the processor based at least on the accessed contents and a pristine copy of the contents; and
based at least on the actual performance exceeding the target performance by a bound amount, triggering a remediation process for the characterized memory.

11. The computerized method of claim 10 , wherein the determining the actual performance with the processor based at least on the accessed contents and the pristine copy of the contents further comprises identifying uncorrectable faults.

12. The computerized method of claim 11 , wherein the remediation process comprises causing a replacement of the characterized memory based at least on the uncorrectable faults exceeding a threshold amount.

13. The computerized method of claim 11 , wherein the remediation process comprises refreshing the contents of the characterized memory based at least on the uncorrectable faults not exceeding a threshold amount.

14. The computerized method of claim 10 , wherein the determining the actual performance with the processor based at least on the accessed contents and the pristine copy of the contents further comprises identifying correctable faults.

15. The computerized method of claim 14 , further comprising repairing the correctable faults.

16. A computerized apparatus configured to remedy faults in one or more characterized memories, the computerized apparatus comprising:
a characterized memory comprising one or more uncorrectable faults, the characterized memory (i) configured to accumulate one or more correctable faults probabilistically during use, and (ii) characterized by a target performance level based at least on a solution density function for an error-tolerant application;
a processor configured to access the characterized memory at a characteristic rate; and
controller logic configured to, when executed by the processor, determine a performance metric based at least on the one or more uncorrectable faults and the one or more correctable faults;
wherein the controller logic is configured to:
refresh the characterized memory based at least on a number of correctable faults exceeding a first threshold;
flag the characterized memory for replacement based at least on a number of uncorrectable faults exceeding a second threshold; and
re-characterize the characterized memory with another target performance level based at least on the determined performance metric.

17. The computerized apparatus of claim 16 , wherein the one or more uncorrectable faults comprise probabilistic errors and hardware failures that (i) cannot be repaired or (ii) exceed a limitation of error correcting capability.

18. The computerized apparatus of claim 16 , wherein the controller logic is further configured to fuse replacement cells to repair hardware failures.

19. The computerized apparatus of claim 16 , wherein the controller logic is further configured to correct errors with an error correcting code.

20. The computerized apparatus of claim 16 , further comprising a pristine memory; and
wherein the controller logic is configured to refresh the characterized memory with data stored the pristine memory.

Assignees

• Micron Technology Inc

Inventors

• Harms Jonathan D

Classifications

• G06F21/64

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• H04L9/50

  using hash chains, e.g. blockchains or hash trees · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title