Display, LED chip therefor, pixel therefor, controlling method therefor, computer program therefor

Patent metadata

Field	Value
Publication number	US-10957241-B2
Application number	US-201916707890-A
Country	US
Kind code	B2
Filing date	Dec 9, 2019
Priority date	Oct 22, 2014
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A display (100) comprising a plurality of LED chips (604), each LED chip (604) comprising a plurality of light emitting elements (606a-c). Each LED chip (604) is arranged such that a first light emitting element (606a) is configured to illuminate a sub-pixel, and a second light emitting element (606b) is configured to illuminate a sub-pixel using substantially the same wavelength of light as the first light emitting element. There is also described an LED chip, a display pixel, a controlling method, a computer device and a computer program for a display.

First claim

The invention claimed is:

1. A display comprising:
a substrate;
a first light emitting diode (LED) chip including a plurality of first light emitting elements; and
a second LED chip including a plurality of second light emitting elements, the first and second light emitting elements configured to emit light having the same wavelength, the first and second LED chips being separate pieces of semiconductor material that are each attached to the substrate, a first light emitting element from the first LED chip and a second light emitting element from the second LED chip arranged to form a sub-pixel with two light emitting elements of the same color for a display pixel of the display,
wherein the first LED chip is triangular and a first light emitting element of the plurality of first light emitting elements is located at each corner of the first LED chip, and
wherein the display pixel is hexagonal.

2. The display of claim 1 , wherein the first LED and second LED chips include the same type of semiconductor material.

3. The display of claim 1 , wherein the first LED chip comprises a plurality of Addressable Array Elements, each Addressable Array Element providing a first light emitting element of the plurality of first light emitting elements.

4. The display of claim 1 , wherein the substrate configured to provide control and power to the first LED chip.

5. The display of claim 4 , wherein the substrate includes an active matrix.

6. The display of claim 4 , wherein the substrate includes a passive matrix.

7. The display of claim 1 , further comprising an optical film disposed over the first LED chip, the optical film configured to direct light from the plurality of first light emitting elements.

8. The display of claim 7 , wherein the optical film is configured to direct the light to a center of the display pixel.

9. The display of claim 1 , wherein the first LED chip is located at an intersection of three adjacent display pixels.

10. The display of claim 1 , wherein the plurality of first light emitting elements of the first LED chip share a common cathode.

11. The display of claim 1 , wherein the first LED chip is located at a corner of the display pixel.

12. The display of claim 1 , further comprising a third LED chip including plurality of third light emitting elements configured to emit light having a different wavelength from the plurality of first light emitting elements of the first LED chip and the plurality of second light emitting elements of the second LED chip, the display pixel including a third light emitting element from the third LED chip.

13. The display of claim 1 , further comprising a processor configured to provide power to one of the first or second light emitting elements.

14. The display of claim 13 , wherein the processor is configured to provide power to the first light emitting element responsive to a failure in the second light emitting element.

15. The display of claim 1 , further comprising a third LED chip including a third light emitting element having quantum dot phosphors, the third light emitting element arranged to form a second sub-pixel of the display pixel.

Assignees

• Facebook Tech Llc

Inventors

• Hughes Padraig
• Henry William
• O'Keeffe Joseph

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/819

  characterised by their shape, e.g. curved or truncated substrates · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title