Signal processing device and method

Patent metadata

Field	Value
Publication number	US-10956154-B2
Application number	US-201515741670-A
Country	US
Kind code	B2
Filing date	Jul 7, 2015
Priority date	Jul 7, 2015
Publication date	Mar 23, 2021
Grant date	Mar 23, 2021

Abstract

A signal processing apparatus includes a memory; a processor comprising arithmetic logic units (ALUs); and a hardware accelerator configured to perform an arithmetic logic operation by using shared ALUs that are not used by the processor among the ALUs.

First claim

The invention claimed is:

1. A signal processing apparatus comprising:
a memory;
a processor comprising an array of shared arithmetic logic units (ALUs); and
a hardware accelerator configured to:
identify shared ALUs that are not currently used by the processor, and
perform an arithmetic logic operation by using one or more of the identified shared ALUs that are not used by the processor among the shared ALUs,
wherein the array of shared ALUs is configured to allow selective use of each shared ALU of the array.

2. The signal processing apparatus of claim 1 ,
wherein the processor further comprises a selector configured to select any one of an input of the processor and an input of the hardware accelerator, and
wherein the selector is connected to an input end of the shared ALUs.

3. The signal processing apparatus of claim 2 , wherein the hardware accelerator further comprises an ALU controller configured to control the shared ALUs and the selector.

4. The signal processing apparatus of claim 3 , wherein the ALU controller is further configured to:
allocate arithmetic logic operations to be performed by the shared ALUs, and
designate an input to be selected by the selector.

5. The signal processing apparatus of claim 1 , wherein during a control operation of the processor, the hardware accelerator is further configured to perform the arithmetic logic operation by using the shared ALUs.

6. The signal processing apparatus of claim 1 , wherein the hardware accelerator is further configured to perform the arithmetic logic operation by using the shared ALUs while the processor is connected to a memory or sets a parameter.

7. The signal processing apparatus of claim 1 , wherein the processor is one of an array processor or a single instruction multiple data (SIMD) processor.

8. The signal processing apparatus of claim 1 , wherein the arithmetic logic operation is at least one of addition, subtraction, multiplication, or division.

9. A signal processing method comprising:
performing a control operation by a processor comprising an array of shared arithmetic logic units (ALUs); and
while the control operation is performed by the processor, identifying shared ALUs that are not currently used by the processor, and
performing an arithmetic logic operation by using one or more of the identified shared ALUs that are not used by the processor among the shared ALUs,
wherein the arithmetic logic operation is performed by a hardware accelerator, and
wherein the array of shared ALUs is configured to allow selective use of each shared ALU of the array.

10. The signal processing method of claim 9 , wherein the performing of the arithmetic logic operation further comprises:
designating arithmetic logic operations to be performed by the shared ALUs;
receiving input values from the hardware accelerator by the shared ALUs; and
performing the designated arithmetic logic operations with respect to the input value by the shared ALUs.

11. The signal processing method of claim 9 ,
wherein the performing of the arithmetic logic operation further comprises, while the processor is connected to a memory or sets a parameter, performing the arithmetic logic operation by using the shared ALUs, and
wherein the arithmetic logic operation is performed by the hardware accelerator.

12. The signal processing method of claim 9 , further comprising:
performing a setting of the hardware accelerator by the processor,
wherein the hardware accelerator performs the arithmetic logic operation after the setting is completed.

13. The signal processing method of claim 9 , further comprising:
performing an arithmetic logic operation by the processor; and
integrating the arithmetic logic operation performed by the processor and the arithmetic logic operation performed by the hardware accelerator.

14. The signal processing method of claim 9 , further comprising:
performing the arithmetic logic operation by using an ALU included in the hardware accelerator,
wherein the arithmetic logic operation is performed by the hardware accelerator.

15. The signal processing method of claim 9 , wherein the hardware accelerator is configured to perform only an independent arithmetic logic operation by using the shared ALUs.

16. A non-transitory computer-readable recording medium having recorded thereon a program which, when executed by a computer, performs the method of claim 9 .

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Won-Jae
• Kim Jae-Hyun

Classifications

• G06F9/30 Primary

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• H04N7/015

  High-definition television systems · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title