Method and circuit for current integration

Patent metadata

Field	Value
Publication number	US-10951222-B2
Application number	US-201816629139-A
Country	US
Kind code	B2
Filing date	Jul 4, 2018
Priority date	Jul 13, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

An input current (Iin) is transformed into an output integrated voltage (Vout_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (Tclk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (Tclk_DAC).

First claim

The invention claimed is:

1. A method of current integration, comprising:
transforming an input current into an output integrated voltage using a parallel connection of an operational transconductance amplifier and an integration capacitor,
reducing the output integrated voltage by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period defining time intervals between successive rising edges of the feedback pulses, and
sampling during an extended feedback clock period after a lapse of a plurality of feedback clock periods.

2. The method of claim 1 , wherein the extended feedback clock period is N times as long as the feedback clock period.

3. The method of claim 1 , further comprising:
reducing a gain-bandwidth product of the operational transconductance amplifier during sampling.

4. The method of claim 1 , further comprising:
performing a range check for the output integrated voltage before sampling, the range check being based on a number of feedback pulses prior to sampling.

5. The method of claim 1 , wherein the digital-to-analog converter is a switched capacitor digital-to-analog converter.

6. The method of claim 1 , wherein the digital-to-analog converter is a switched current source digital-to-analog converter.

7. The method of claim 1 , further comprising:
generating further feedback pulses between the feedback pulses generated by the digital-to-analog converter by applying a further digital-to-analog converter in the feedback loop.

8. A method of current integration, comprising:
transforming an input current into an output integrated voltage using a parallel connection of an operational transconductance amplifier and an integration capacitor,
reducing the output integrated voltage by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses,
applying an electric power for the operational transconductance amplifier, and
elevating the applied electric power only for sampling during a sampling time.

9. A circuit for current integration, comprising:
a parallel connection of an integration capacitor, an operational transconductance amplifier and a feedback loop, the operational transconductance amplifier being configured to transform an input current into an output integrated voltage,
a digital-to-analog converter in the feedback loop, the digital-to-analog converter being configured to generate feedback pulses triggering discharges of the integration capacitor, a feedback clock period defining time intervals between successive rising edges of the feedback pulses, and
a controller configured to provide an extended feedback clock period after a lapse of a plurality of feedback clock periods.

10. The circuit of claim 9 , wherein:
the controller is configured to perform a range check for the output integrated voltage before sampling, the range check being based on a number of feedback pulses prior to sampling.

11. The circuit of claim 9 , wherein the digital-to-analog converter is a switched capacitor digital-to-analog converter.

12. The circuit of claim 9 , wherein the digital-to-analog converter is a switched current source digital-to-analog converter.

13. The circuit of claim 9 , further comprising:
a further digital-to-analog converter in the feedback loop, the controller being configured to enable an alternative operation of the digital-to-analog converter and the further digital-to-analog converter.

14. The method of claim 1 , wherein the extended feedback clock period is provided when an input level of the input current is less than half of a signal range of the input current.

15. The circuit of claim 9 , wherein the controller configured to provide the extended feedback clock period when an input level of the input current is less than half of a signal range of the input current.

Assignees

• Ams Int Ag

Inventors

• Michel Fridolin

Classifications

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• G11C27/024

  using a capacitive memory element (G11C27/04 takes precedence) · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/86

  with intermediate conversion to frequency of pulses · CPC title