Connector with tuned channel

US10950982B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10950982-B2
Application numberUS-201916594110-A
CountryUS
Kind codeB2
Filing dateOct 7, 2019
Priority dateAug 8, 2011
Publication dateMar 16, 2021
Grant dateMar 16, 2021

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A connector is provided that includes a plurality of wafers. Each wafer supports a terminal and adjacent signal wafers are configured so as to provide broad-side coupled terminals. A pair of signal terminals can be surrounded on both sides by ground wafers that offer shielding so as to help isolate one signal pair from another signal pair. The geometry of the wafers can be adjusted so as to provide a tuned transmission channel. The resultant tuned transmission channel can be configured to provide desirable performance at high signaling frequencies of 12-16 GHz or even higher signaling frequencies such as 20 GHz.

First claim

Opening claim text (preview).

We claim: 1. A connector, comprising: a first wafer including a first terminal, the first terminal being a ground terminal; a second wafer positioned adjacent the first wafer, the second wafer including a first truss that supports a second terminal, the second terminal being a signal terminal; a third wafer positioned adjacent the second wafer, the third wafer including a second truss that supports a third terminal, the third terminal being a signal terminal and the second terminal and the third terminal being a differential pair of signal terminals; a fourth wafer positioned adjacent the third wafer, the fourth wafer including a fourth terminal, the fourth terminal being a ground terminal, wherein the first through fourth wafers are in series, and each truss is formed of insulative material and defines a dielectric constant for each of the terminals, wherein the dielectric constant associated with the coupling between the second and third terminals is different than the dielectric constant between the first wafer and second terminal and between the third terminal and the fourth wafer. 2. The connector of claim 1 , wherein the difference in the dielectric constant about the second and third terminals is symmetric. 3. The connector of claim 1 , wherein the trusses are formed by terminal grooves that extend along the trusses and each wafer has a first side and an opposing second side. 4. The connector of claim 3 , wherein the terminal grooves are intersected by ribs on the first side and ribs on the opposing second side. 5. The connector of claim 1 , wherein the connector includes a card slot and the terminals extend to the card slot. 6. The connector of claim 5 , further comprising a cage that defines at least one port aligned with the card slot, the cage having a cage front and a cage rear that are on opposing sides of the cage, the card slot being positioned closer to the cage rear and further away from the cage front. 7. A connector, comprising: a first wafer including a first terminal, the first terminal being a ground terminal; a second wafer positioned adjacent the first wafer, the second wafer including a first truss that supports a second terminal, the second terminal being a signal terminal; a third wafer positioned adjacent the second wafer, the third wafer including a second truss that supports a third terminal, the third terminal being a signal terminal and the second terminal and the third terminal being a differential pair of signal terminals; a fourth wafer positioned adjacent the third wafer, the fourth wafer including a fourth terminal, the fourth terminal being a ground terminal, wherein the first through fourth wafers are in series, and each truss is formed of insulative material and defines a dielectric constant for each of the terminals, wherein the dielectric constant associated with the coupling between the second and third terminals is an inner dielectric constant and the dielectric constant between the first wafer and second terminal and the third terminal and fourth wafer are equivalent to each other but have a value different than that of the inner dielectric constant. 8. The connector of claim 7 , wherein the trusses are formed by terminal grooves that extend along the trusses and each wafer has a first side and an opposing second side. 9. The connector of claim 8 , wherein the terminal grooves are intersected by ribs on the first side and ribs on the opposing second side. 10. The connector of claim 7 , wherein the connector includes a card slot and the terminals extend to the card slot. 11. The connector of claim 10 , further comprising a cage that defines at least one port aligned with the card slot, the cage having a cage front and a cage rear that are on opposing sides of the cage, the card slot being positioned closer to the cage rear and further away from the cage front.

Assignees

Inventors

Classifications

  • H01R9/2408Primary

    Modular blocks (H01R9/26 takes precedence) · CPC title

  • containing contact members forming a right angle · CPC title

  • by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal] · CPC title

  • for separating multiple connector modules · CPC title

  • for rigid printing circuits or like structures · CPC title

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Frequently asked questions

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What does patent US10950982B2 cover?
A connector is provided that includes a plurality of wafers. Each wafer supports a terminal and adjacent signal wafers are configured so as to provide broad-side coupled terminals. A pair of signal terminals can be surrounded on both sides by ground wafers that offer shielding so as to help isolate one signal pair from another signal pair. The geometry of the wafers can be adjusted so as to pro…
Who is the assignee on this patent?
Molex Llc
What technology area does this patent fall under?
Primary CPC classification H01R9/2408. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).