Semiconductor component and method for producing same

Patent metadata

Field	Value
Publication number	US-10947109-B2
Application number	US-201816142826-A
Country	US
Kind code	B2
Filing date	Sep 26, 2018
Priority date	Oct 5, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A method for producing a semiconductor component is proposed. The method includes providing a housing. At least one semiconductor chip is arranged in a cavity of the housing. Furthermore, an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire. The method furthermore includes applying a protective material on the electrical contact of the semiconductor chip and also on a region of the bond wire which is adjacent to the electrical contact of the semiconductor chip, and/or on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing. Moreover, the method also includes filling at least one partial region of the cavity with a gel.

First claim

What is claimed is:

1. A method for producing a semiconductor component, the method comprising:
providing a housing, wherein at least one semiconductor chip is arranged in a cavity of the housing, and wherein an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire;
applying a protective material at a first region including on the electrical contact of the semiconductor chip and also on a region of the bond wire which is adjacent to the electrical contact of the semiconductor chip, and applying the protective material at a second region including on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing, wherein the first region and the second region are separated by a gap; and
filling at least one partial region of the cavity, including the gap, with a gel.

2. The method as claimed in claim 1 , wherein the region of the bond wire which is adjacent to the electrical contact of the semiconductor chip extends over less than 30% of a length of the bond wire, and wherein the region of the bond wire which is adjacent to the electrical contact of the housing extends over less than 30% of the length of the bond wire.

3. The method as claimed in claim 1 , wherein the protective material is an epoxy resin.

4. The method as claimed in claim 1 , wherein the semiconductor chip is a MicroElectroMechanical System (MEMS) sensor.

5. The method as claimed in claim 4 , wherein the MEMS sensor is a pressure sensor.

6. The method as claimed in claim 1 , wherein the electrical contact of the housing delimits the cavity.

7. The method as claimed in claim 1 , wherein filling at least the partial region of the cavity with the gel comprises completely encapsulating the semiconductor chip, the electrical contact of the housing, and the bond wire with the gel.

8. The method as claimed in claim 1 , wherein applying the protective material comprises dispensing or jetting the protective material.

9. The method as claimed in claim 1 , wherein applying the protective material comprises:
depositing the protective material into the cavity;
forming a photoresist structure;
etching a part of the protective material that is not covered by the photoresist structure; and
removing the photoresist structure.

10. The method as claimed in claim 1 , wherein providing the housing comprises forming a sidewall and an elevation structure in the housing, wherein the elevation structure at least partly borders the electrical contact of the housing, and
wherein applying the protective material on the electrical contact of the housing and also on the region of the bond wire which is adjacent to the electrical contact of the housing comprises introducing the protective material into a space located above the electrical contact of the housing between the elevation structure and the sidewall.

11. The method as claimed in claim 10 , wherein forming the elevation structure in the housing is carried out before arranging the semiconductor chip in the housing.

12. The method as claimed in claim 10 , wherein forming the elevation structure in the housing is carried out after arranging the semiconductor chip in the housing.

13. The method as claimed in claim 1 , further comprising:
forming an elevation structure on the semiconductor chip, wherein the elevation structure at least partly borders the electrical contact of the semiconductor chip, and
wherein applying the protective material on the electrical contact of the semiconductor chip and also on the region of the bond wire which is adjacent to the electrical contact of the semiconductor chip comprises introducing the protective material into a space enclosed by the elevation structure, above the electrical contact of the semiconductor chip.

14. The method as claimed in claim 1 , wherein the gel is a silicone gel.

15. The method as claimed in claim 1 , wherein filling the at least one partial region of the cavity, including the gap, with the gel includes applying the gel on a portion of the bond wire arranged between the first region and the second region.

16. The method as claimed in claim 15 , wherein the portion of the bond wire arranged between the first region and the second region is encapsulated by the gel.

17. A semiconductor component, comprising:
a housing; and
a semiconductor chip arranged in a cavity of the housing,
wherein an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire;
wherein a protective material is applied at a first region including on the electrical contact of the semiconductor chip and also on a region of the bond wire which is adjacent to the electrical contact of the semiconductor chip, and the protective material is applied at a second region including on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing,
wherein the first region and the second region are separated by a gap,
wherein at least one partial region of the cavity, including the gap, is filled with a gel.

18. The semiconductor component as claimed in claim 17 , wherein the region of the bond wire which is adjacent to the electrical contact of the semiconductor chip extends over less than 30% of a length of the bond wire, and wherein the region of the bond wire which is adjacent to the electrical contact of the housing extends over less than 30% of the length of the bond wire.

19. The semiconductor component as claimed in claim 17 , wherein the protective material is an epoxy resin.

20. The semiconductor component as claimed in claim 17 , wherein the semiconductor chip is a MicroElectroMechanical System (MEMS) sensor.

21. The semiconductor component as claimed in claim 17 , wherein the electrical contact of the housing delimits the cavity.

22. The semiconductor component as claimed in claim 17 , wherein the housing includes a sidewall, the semiconductor component further comprising:
a first elevation structure formed in the housing, wherein the first elevation structure at least partly borders the electrical contact of the housing,
wherein the protective material is introduced into a space located above the electrical contact of the housing between the first elevation structure and the sidewall, and
wherein the electrical contact of the semiconductor chip is at least partly bordered by a second elevation structure and the protective material is introduced into a space enclosed by the second elevation structure, above the electrical contact of the semiconductor chip.

23. The semiconductor component as claimed in claim 17 , wherein the gel is applied directly on a portion of the bond wire arranged between the first region and the second region.

24. The semiconductor component as claimed in claim 23 , wherein the portion of the bond wire arranged between the first region and the second region is encapsulated by the gel.

Assignees

• Infineon Technologies Ag

Inventors

• Vaupel Mathias
• Knott Bernhard
• Theuss Horst

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/583

  Reinforcing structures · CPC title

• H10W72/07553

  changes in shapes · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title