Geometry tuning of fin based transistor

Patent metadata

Field	Value
Publication number	US-10944006-B2
Application number	US-201616070262-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.

First claim

What is claimed is:

1. A method to manufacture an electronic device comprising:
forming a first trench in an insulating layer to expose a native fin on a substrate;
depositing a replacement fin on the native fin in the trench; and
trimming the replacement fin laterally using a first chemistry.

2. The method of claim 1 , wherein trimming comprises adjusting the width of the replacement fin based on the width of the native fin.

3. The method of claim 1 , wherein the replacement fin is trimmed laterally using an isotropic etch.

4. The method of claim 1 , wherein the first chemistry comprises fluorine, chlorine, bromine, or any combination thereof.

5. The method of claim 1 , wherein the first chemistry comprises an ammonium hydroxide and water, wherein a ratio of water to the ammonium hydroxide is at least 1000:1.

6. The method of claim 1 , further comprising etching a second trench in the substrate to form the native fin; depositing the insulating layer into the second trench; and recessing the native fin to deposit the replacement fin.

7. The method of claim 1 , wherein the trimming is to reduce the replacement fin width to be narrower than or equal to the native fin width.

8. A method to manufacture an electronic device comprising:
forming a plurality of native fins on a substrate, each native fin extending from the substrate;
depositing an insulating layer on the plurality of native fins;
recessing a first set of the native fins to provide a first set of trenches;
depositing first replacement fins in the first set of trenches;
recessing the insulating layer; and
trimming the first replacement fins laterally.

9. The method of claim 8 , further comprising depositing a first protection layer on a second set of the fins.

10. The method of claim 8 , further comprising recessing a second set of the native fins to provide a second set of trenches; depositing second replacement fins in the second set of trenches; and
trimming the second replacement fins laterally.

11. The method of claim 8 wherein trimming comprises adjusting the width of the replacement fins based on the width of the native fins.

12. The method of claim 8 , wherein the first replacement fins are trimmed laterally using an isotropic etch.

13. The method of claim 8 , wherein the first replacement fins are trimmed laterally using at least one of a plasma etch at a source power less than 2000 W, or a remote plasma source.

14. The method of claim 8 , wherein at least one of the first replacement fins is a germanium fin, a silicon germanium fin, a germanium tin fin, a III-V material fin, or any combination thereof.

15. An electronic device, comprising:
a first trench in an insulating layer that exposes a native fin on a substrate;
a replacement fin on the native fin in the trench, wherein the width of the replacement fin is narrower than the width of the native fin.

16. The electronic device of claim 15 , wherein an interface between the native fin and the replacement fin is substantially flat.

17. The electronic device of claim 15 , wherein the replacement fin is a germanium fin, a silicon germanium fin, a germanium tin fin, a III-V material fin, or any combination thereof.

18. The electronic device of claim 15 , wherein the native fin is a silicon fin.

19. The electronic device of claim 15 , wherein the width of the replacement fin is less than 5 nm.

20. The electronic device of claim 15 , further comprising a gate structure on the replacement fin; and
source/drain regions at opposite sides of the gate structure.

21. An electronic device, comprising:
a first trench in an insulating layer that exposes a native fin on a substrate;
a replacement fin on the native fin in the trench, wherein the width of the replacement fin is narrower or equal to the width of the native fin, and wherein the width of the replacement fin is less than 5 nm.

Assignees

• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S
• Jambunathan Karthik
• Mohapatra Chandra S
• Kam Hei
• Mistkawi Nabil G
• Kang Jun Sung
• Guha Biswajeet

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title