Method of fabricating a plurality of linear arrays with submicron y-axis alignment

Patent metadata

Field	Value
Publication number	US-10943895-B2
Application number	US-201916247016-A
Country	US
Kind code	B2
Filing date	Jan 14, 2019
Priority date	Jan 14, 2019
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

A method of assembling a plurality of linear arrays from a silicon wafer having a first surface and a second surface opposite the first surface, the first surface having at least a first linear array of sensor/emitter elements and a second linear array of sensor/emitter elements, each arranged parallel relative to a first direction, and a sacrificial portion positioned between the first linear array of sensor/emitter elements and the second linear array of sensor/emitter elements. The method includes: forming a first cavity in the second surface positioned opposite the sacrificial portion and parallel relative to the first direction; forming at least a first through cut, a second through cut, a third through cut and a fourth through cut in the silicon wafer, the first and second through cuts are parallel to the first direction, the third and fourth through cuts are perpendicular to the first direction, the first through cut arranged adjacent to the first linear array of sensor/emitter elements opposite the sacrificial portion, the second through cut arranged adjacent to the second linear array of sensor/emitter elements opposite the sacrificial portion, and the third and fourth through cuts form a first end and a second end, respectively, of a multi-row sensor/emitter chip defined by the first, second, third and fourth through cuts; bonding at least a portion of the multi-row sensor/emitter chip formed by the second surface of the silicon wafer to a mounting substrate; and, removing the sacrificial portion.

First claim

What is claimed is:

1. A method of assembling a dual linear sensor array from a silicon wafer comprising a first surface and a second surface opposite the first surface, the first surface comprising at least a first linear array of sensor elements and a second linear array of sensor elements, each arranged parallel relative to a first direction, and a sacrificial portion positioned between the first linear array of sensor elements and the second linear array of sensor elements, the method comprising:
forming a first reference through cut in the first surface parallel to the first direction;
forming a second reference through cut in the first surface perpendicular to the first direction;
forming a first cavity in the second surface positioned opposite the sacrificial portion and parallel relative to the first direction, the position of the first cavity being defined by a position of the first reference through cut;
forming at least a first through cut, a second through cut, a third through cut and a fourth through cut in the silicon wafer, the first and second through cuts are parallel to the first direction, the third and fourth through cuts are perpendicular to the first direction, the first through cut arranged adjacent to the first linear array of sensor elements opposite the sacrificial portion, the second through cut arranged adjacent to the second linear array of sensor elements opposite the sacrificial portion, and the third and fourth through cuts form a first end and a second end, respectively, of a multi-row sensor chip defined by the first, second, third and fourth through cuts;
forming a second cavity in the second surface perpendicular to the first direction, wherein a position of the second cavity is defined by a position of the second reference through cut;
bonding at least a portion of the multi-row sensor chip formed by the second surface of the silicon wafer to a mounting substrate; and,
removing the sacrificial portion.

2. The method of claim 1 further comprising:
forming at least a first column partial through cut in the first surface positioned generally opposite the second cavity and perpendicular to the first direction.

3. The method of claim 1 further comprising:
repeating the step of forming the first through cut, the second through cut, the third through cut and the fourth through cut at unique locations in the silicon wafer, thereby forming a plurality of multi-row sensor chips, each of the plurality of multi-row sensor chips comprises a first linear array of sensor elements and a second linear array of sensor elements, each arranged parallel relative to a first direction, and a sacrificial portion;
bonding at least a portion of each of the plurality of multi-row sensor chips formed by the second surface of the silicon wafer adjacently to the mounting substrate; and,
removing each of the plurality of sacrificial portions.

4. The method of claim 1 wherein the mounting substrate comprises at least a first row of electrical connectors and a second row of electrical connectors parallel to the first row, and the step of bonding at least a portion of the multi-row sensor chip formed by the second surface of the silicon wafer to the mounting substrate results in aligning the sacrificial portion over the second row of electrical connectors.

5. The method of claim 1 wherein at least one of: the step of forming the first cavity; and, the step of forming at least the first through cut, the second through cut, the third through cut and the fourth through cut, is performed by mechanical abrasion, laser cutting, chemical etching, or a combination thereof.

6. The method of claim 1 further comprising:
bonding at least one first wire between a first electrical connector on the mounting substrate and the first linear array of sensor elements; and,
bonding at least one second wire between a second electrical connector on the mounting substrate and the second linear array of sensor elements.

7. The method of claim 1 wherein the step of removing the sacrificial portion comprises:
forming a fifth through cut positioned generally opposite the first cavity and parallel relative to the first direction, the fifth through cut arranged between the first linear array of sensor elements and the sacrificial portion; and,
forming a sixth through cut positioned generally opposite the first cavity and parallel relative to the first direction, the fifth through cut arranged between the second linear array of sensor elements and the sacrificial portion.

8. The method of claim 1 , prior to the step of bonding, further comprising:
forming at least a first street partial through cut and a second street partial through cut in the first surface positioned generally opposite the first cavity and parallel relative to the first direction, the first street partial through cut arranged between the first linear array of sensor elements and the sacrificial portion, and the second street partial through cut arranged between the second linear array of sensor elements and the sacrificial portion.

9. The method of claim 8 wherein the step of removing the sacrificial portion comprises:
cleaving the sacrificial portion along the first street partial through cut and along the second street partial through cut.

10. The method of claim 8 further comprising:
forming at least a third street partial through cut in the first surface positioned generally opposite the first cavity and parallel relative to the first direction, the third street partial through cut arranged between the first street partial through cut and the second street partial through cut.

11. The method of claim 1 wherein the sacrificial portion comprises a third linear array of sensor elements.

12. A method of assembling a dual linear light emitting array from a silicon wafer comprising a first surface and a second surface opposite the first surface, the first surface comprising at least a first linear array of light emitting elements and a second linear array of light emitting elements, each arranged parallel relative to a first direction, and a sacrificial portion positioned between the first linear array of light emitting elements and the second linear array of light emitting elements, the method comprising:
forming a first cavity in the second surface positioned opposite the sacrificial portion and parallel relative to the first direction;
forming at least a first through cut, a second through cut, a third through cut and a fourth through cut in the silicon wafer, the first and second through cuts are parallel to the first direction, the third and fourth through cuts are perpendicular to the first direction, the first through cut arranged adjacent to the first linear array of light emitting elements opposite the sacrificial portion, the second through cut arranged adjacent to the second linear array of light emitting elements opposite the sacrificial portion, and the third and fourth through cuts form a first end and a second end, respectively, of a multi-row light emitting chip defined by the first, second, third and fourth through cuts;
bonding at least a portion of the multi-row light emitting chip formed by the second surface of the silicon wafer to a mounting substrate, the mounting substrate comprising at least a first row of electrical connectors and a second row of electrical connectors parallel to the first row, and the step of bonding at least a portion of the multi-row light emitting chip formed by the second surface of the silicon wafer to the mounting substrate results in aligning the sacrificial portion over the second row of electrical connectors; and,
removing the sacrificial portion.

Assignees

• Xerox Corp

Inventors

• Redding Gary D
• Casey Joseph F

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/075

  of bond wires · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title