Thin-film transistor array substrate and electronic device including the same

Patent metadata

Field	Value
Publication number	US-10943546-B2
Application number	US-201916694674-A
Country	US
Kind code	B2
Filing date	Nov 25, 2019
Priority date	Dec 10, 2018
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

An electronic device includes a panel including first and second transistors and a driver circuit driving the panel. The first transistor includes a first electrode disposed on a substrate, a first insulating film disposed on the substrate and having an open area, a second electrode disposed on the first insulating film and overlapping the first electrode, and a first active layer disposed on the first and second electrodes. The second transistor includes third and fourth electrodes which are disposed to space apart from, and on a same layer as, the second electrode, and between which the open area is disposed, and a second active layer disposed on the third and fourth electrodes and across the open area.

First claim

What is claimed is:

1. An electronic device comprising:
a panel;
a driver circuit configured to drive the panel; and
first and second transistors disposed in the panel, the first and second transistors including:
a first electrode of the first transistor, the first electrode being disposed on a substrate;
a first insulating film disposed on the substrate, overlapping an edge of the first electrode and having an open area for receiving portions of the second transistor;
a second electrode of the first transistor, the second electrode being disposed on the first insulating film and overlapping with a portion of the first electrode;
third and fourth electrodes of the second transistor, the third electrode and the fourth electrode being disposed on a same layer as the second electrode and spaced apart from the second electrode, the open area of the first insulating film being disposed between the third electrode and the fourth electrode;
a first active layer of the first transistor, the first active layer being disposed on the first electrode, the first insulating film and the second electrode; and
a second active layer of the second transistor, the second active layer being disposed on the third and fourth electrodes and across the open area of the first insulating film.

2. The electronic device according to claim 1 , further comprising:
a second insulating film disposed on the first active layer, the second active layer and the third electrode; and
a first gate electrode of the first transistor and a second gate electrode of the second transistor, the first gate electrode being disposed on the second insulating film and overlapping with the first active layer, and the second gate electrode being disposed on the second insulating film and overlapping with the second active layer.

3. The electronic device according to claim 1 , wherein the first active layer includes a first channel area disposed along a side surface of the first insulating film, and
wherein the first channel area is non-parallel to the substrate.

4. The electronic device according to claim 1 , wherein a plurality of data lines intersect a plurality of gate lines within the panel, and
wherein the first active layer of the first transistor overlaps one data line among the plurality of data lines and one gate line among the plurality of gate lines.

5. The electronic device according to claim 2 , further comprising:
a first plate of a storage capacitor integral with the third electrode;
a second plate of the storage capacitor disposed on the first plate;
a third insulating film disposed on the second plate; and
a third plate of the storage capacitor disposed on the third insulating film.

6. The electronic device according to claim 5 , wherein the first plate and the third plate are electrically connected to each other via a first hole extending through the second and third insulating films.

7. The electronic device according to claim 5 , wherein the second plate is integral with the second gate electrode of the second transistor.

8. The electronic device according to claim 5 , wherein the second insulating film is denser than the first insulating film, and
wherein the second insulating film has less thickness variation than the first insulating film, or the second insulating film has a more uniform thickness than the first insulating film.

9. The electronic device according to claim 2 , wherein one of the first and second electrodes of the first transistor is electrically connected to both the second gate electrode of the second transistor and a storage capacitor.

10. The electronic device according to claim 1 , wherein the second transistor is configured to receive a data voltage.

11. The electronic device according to claim 1 , wherein the first active layer includes a first channel area, and
wherein the first channel area contacts a side surface of the first insulating film.

12. The electronic device according to claim 2 , wherein the second active layer includes a conductive area, the conductive area non-overlapping with the second gate electrode, and
wherein the conductive area of the second active layer includes at least one sloped area.

13. The electronic device according to claim 12 , wherein the at least one sloped area includes a region corresponding to at least one side of the third or fourth electrodes of the second transistor.

14. The electronic device according to claim 1 , wherein the second gate electrode is disposed closer to the substrate than the third and fourth electrodes of the second transistor.

15. The electronic device according to claim 2 , wherein the panel further includes a third transistor disposed on the substrate, the third transistor including:
a fifth electrode disposed on the substrate;
the first insulating film exposing an edge of the fifth electrode and a portion of a top surface of the substrate;
a sixth electrode disposed on the first insulating film;
a third active layer disposed on the sixth electrode, the first insulating film and the fifth electrode, the third active layer of the third transistor including a third channel area contacting a side surface of the first insulating film; and
a third gate electrode disposed on the second insulating film and overlapping with the third active layer.

16. The electronic device according to claim 15 , wherein one of the fifth and sixth electrodes of the third transistor is electrically connected to the third electrode or the fourth electrode of the second transistor.

17. The electronic device according to claim 15 , wherein a plurality of reference voltage lines are disposed within the panel to be parallel to a plurality of data lines intersecting a plurality of gate lines, and
wherein the third active layer overlaps with one reference voltage line among the plurality of reference voltage lines and one gate line among the plurality of gate lines.

18. The electronic device according to claim 17 , wherein the fifth electrode of the third transistor is integral with the one reference voltage line overlapped with the third active layer.

19. The electronic device according to claim 17 , wherein the one gate line overlapped with the third active layer also overlaps with the first active layer.

20. The electronic device according to claim 17 , wherein the third active layer and the first active layer overlap with different gate lines among the plurality of gate lines.

21. The electronic device according to claim 15 , wherein each of a plurality of subpixels in an active area of the panel includes the first, second and third transistors.

22. The electronic device according to claim 21 , further comprising:
a third insulating film disposed on the third and fourth electrodes of the second transistor; and
a pixel electrode disposed on the third insulating film, the pixel electrode being electrically connected to the third or fourth electrode via a second hole in the second and third insulating films.

23. The electronic device according to claim 15 , wherein at least one transistor among the first, second, and third transistors is included in a gate driver circuit disposed in a non-active area in a periphery of an active area of the panel.

24. A thin-transistor array substrate comprising:
a substrate;
a first electrode of a first transistor being disposed on the substrate;
a first insulating film disposed on the substrate, overlapping an edge of the first electr

Assignees

• Lg Display Co Ltd

Inventors

• Cho Intak
• Yun Pilsang
• Jeon Jeyong
• Noh Jiyong
• Park Sehee

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title