Loss of signal detection circuit

Patent metadata

Field	Value
Publication number	US-10938385-B2
Application number	US-202016936462-A
Country	US
Kind code	B2
Filing date	Jul 23, 2020
Priority date	Aug 9, 2018
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

First claim

What is claimed is:

1. A LOS (loss of signal) detector circuit comprising:
a first differential comparator having a first input, a second input, and an output;
a second differential comparator having a first input coupled to the second input of the first differential comparator, a second input coupled to the first input of the first differential comparator, and an output;
a first switched latch circuit having a first input coupled to the output of the first differential comparator, a second input coupled to the output of the second differential comparator and a control input;
a first inverter having an input coupled to the output of the first differential comparator and an output;
a second inverter having an input coupled to the output of the second differential comparator and an output; and
a first logic circuit having a first input coupled to the output of the first inverter, a second input coupled to the output of the second inverter and an output.

2. The LOS detector circuit of claim 1 , further comprising a second switched latch circuit coupled to the output of the first inverter and to the output of the second inverter.

3. The LOS detector circuit of claim 1 , wherein the first logic circuit comprises an inverting AND (NAND) logic circuit.

4. The LOS detector circuit of claim 3 , further comprising a third inverter having an input coupled to the output of the first logic circuit and an output.

5. The LOS detector circuit of claim 1 , further comprising:
a second logic circuit having a first input coupled to the output of the first differential comparator, a second input coupled to the output of the second differential comparator and an output;
a resistor having a first terminal coupled to the output of the second logic circuit and a second terminal; and
a capacitor having a first terminal coupled the second terminal of the resistor and a second terminal coupled to ground.

6. The LOS detector circuit of claim 5 , wherein a switch control signal is generated at the first terminal of the capacitor and coupled to the control input of the first switched latch circuit, and wherein the switch control signal controls enablement and disablement of the first switched latch circuit.

7. The LOS detector circuit of claim 1 , wherein the first switched latch circuit comprises:
a first switch having a first terminal coupled to the output of the first differential comparator, a second terminal, and a third terminal coupled to the control input;
a second switch having a first terminal coupled to the output of the second differential comparator, a second terminal and a third terminal coupled to the control input;
a fourth inverter having an input coupled to the second terminal of the first switch and an output coupled to the second terminal of the second switch; and
a fifth inverter having an input coupled to the second terminal of the second switch and an output coupled to the second terminal of the first switch.

8. A method for reducing false LOS (loss of signal) triggers comprising:
determine magnitudes of components of a differential input signal provided to inputs of first and second differential comparators;
generate a LOS signal when the magnitudes of the components of the differential signal are all below a threshold voltage;
generate a switch control signal when any of the components of the differential signal are above the threshold voltage;
apply positive feedback to a signal across an output of the first differential comparator and an output of the second differential comparator when the switch control is generated;

generate the LOS signal based on the signal across the output of the first differential comparator and the output of the second differential comparator after positive feedback has been applied.

Assignees

• Texas Instruments Inc

Inventors

• Huang Huanzhang
• Rane Amit

Classifications

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• H03K17/56

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title

• G06F13/382 Primary

  using universal interface adapter · CPC title

• H03K17/005 Primary

  with several inputs only · CPC title