Power amplifier and method of operating the power amplifier

Patent metadata

Field	Value
Publication number	US-10938359-B1
Application number	US-201916574633-A
Country	US
Kind code	B1
Filing date	Sep 18, 2019
Priority date	Aug 13, 2019
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.

First claim

What is claimed is:

1. A power amplifier, comprising:
an operational amplifier configured to output a positive amplifying output and a negative amplifying output based on a positive input and a negative input;
a ramp generator communicatively coupled to both negative inputs of a first comparator and a second comparator, and configured to generate a ramp signal;
a positive input port of the first comparator is further communicatively coupled to a negative output port of the operational amplifier and the first comparator is further configured to generate a first decision result by comparing the first negative output of the operational amplifier and the ramp signal;
a positive input port of the second comparator is further communicatively coupled to a positive output port of the operational amplifier and the second comparator is further configured to generate a second decision result by comparing the first positive output of the operational amplifier and the ramp signal;
a first inverter communicatively coupled to the first comparator and configured to output a first inverted output by inverting the first decision result;
a second inverter communicatively coupled to the second comparator and configured to output a second inverted output by inverting the second decision result;
an output port of the first inverter is communicatively coupled to both the positive input port of the operational amplifier via a first resistor and connected to the negative input port of the operational amplifier via a fourth resistor and configured to feed the first inverted output back to the positive input port of the operational amplifier and the negative input port of the operational amplifier; and
an output port of the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor and configured to feed the second inverted output back to the positive input port of the operational amplifier and the negative input port of the operational amplifier.

2. The power amplifier of claim 1 , wherein the first inverter comprises a first PMOS transistor and a first NMOS transistor, and the second inverter comprises a second PMOS transistor and a second NMOS transistor;
a source of the first PMOS transistor is connected to a power supply, and a gate of the first PMOS transistor is connected to an output of the first comparator, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor, to both the positive input port of the operational amplifier via the first resistor and the negative input port of the operational amplifier via the fourth resistor;
a gate of the first NMOS transistor is connected to the output of the first comparator, and a source of the first NMOS transistor is connected to the ground;
a source of the second PMOS transistor is connected to the power supply, and a gate of the second PMOS transistor is connected to an output of the second comparator, and a drain of the second PMOS transistor is connected to a drain of the second NMOS transistor, to both the positive input port of the operational amplifier via the second resistor and the negative input port of the operational amplifier via the third resistor; and
a gate of the second NMOS transistor is connected to the output of the second comparator, and a source of the second NMOS transistor is connected to the ground.

3. The power amplifier of claim 1 , further comprising
a first buffer communicatively coupled to an output of the first comparator and the first inverter and configured to generate a negative output voltage by buffering the first decision result;
a second buffer communicatively coupled to an output of the second comparator and the second inverter and configured to generate a positive output voltage by buffering the second decision result;
wherein the first inverter is further configured to output the first inverted output by inverting the negative output voltage; and
the second inverter is further configured to output the second inverted output by inverting the positive output voltage.

4. The power amplifier of claim 3 , wherein the first buffer comprises a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor, wherein
a source of the third PMOS transistor is connected to the power supply, and a gate of the third PMOS transistor is connected to the output of the first comparator, and a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor, a gate of the fourth PMOS transistor and a gate of the fourth NMOS transistor;
a gate of the third NMOS transistor is connected to the output of the first comparator, and a source of the third NMOS transistor is connected to a ground;
a source of the fourth PMOS transistor is connected to the power supply, and a drain of the fourth PMOS transistor is connected to a drain of the fourth NMOS transistor and configured to output the negative output voltage; and
a source of the fourth NMOS transistor is connected to the ground.

5. The power amplifier of claim 4 , wherein the second buffer comprises a fifth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor and a sixth NMOS transistor, wherein
a source of the fifth PMOS transistor is connected to the power supply, and a gate of the fifth PMOS transistor is connected to the output of the second comparator, and a drain of the fifth PMOS transistor is connected to a drain of the fifth NMOS transistor, a gate of the sixth PMOS transistor and a gate of the sixth NMOS transistor;
a gate of the fifth NMOS transistor is connected to the output of the second comparator, and a source of the fifth NMOS transistor is connected to a ground;
a source of the sixth PMOS transistor is connected to the power supply, and a drain of the sixth PMOS transistor is connected to a drain of the sixth NMOS transistor and configured to output the positive output voltage; and
a source of the sixth NMOS transistor is connected to the ground.

6. The power amplifier of claim 3 , wherein the output port of the first buffer is further communicatively coupled to a positive input port of the operational amplifier, and the output port of the second buffer is further communicatively coupled to a positive input port of the operational amplifier.

7. The power amplifier of claim 1 , wherein the output port of the first comparator is further communicatively coupled to the positive input port of the operational amplifier via a first reference resistor, and the output port of the second comparator is further communicatively coupled to the positive input port of the operational amplifier via a second reference resistor.

8. The power amplifier of claim 1 , wherein the ramp generator is a triangle wave generator.

9. The power amplifier of claim 1 , wherein the ramp generator is a jigsaw wave generator.

10. A method of operating a power amplifier, comprising:
outputting, by an operational amplifier, a positive amplifying output and a negative amplifying output based on a positive input and a negative input;
generating, by a ramp generator communicatively coupled to both negative inputs of a first comparator and a second comparator, a ramp signal;
generating, by the first comparator communicatively coupled to a negative output port of the operational amplifier, a first decision result by comparing the negative amplifying output of the operational amplifier and the ramp signal;
generating, by the second comparator communicatively coupled to a positive output port of the operational amplifier and the second comparator, a second decis

Assignees

• Beken Corp

Inventors

• Liu Jiazhou
• Gao Donghui

Classifications

• H03F3/2178

  using more than one switch or switching amplifier in parallel or in series (H03F3/2173, H03F3/2175 take precedence) · CPC title

• H03F3/2171 Primary

  with field-effect devices (H03F3/2173 - H03F3/2178 take precedence) · CPC title

• H03F2203/45594

  the IC comprising one or more resistors, which are not biasing resistor · CPC title

• H03F2203/45512

  the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title