Banknote processing machine having power control electronics

US10937266B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10937266-B2
Application numberUS-201515532955-A
CountryUS
Kind codeB2
Filing dateDec 2, 2015
Priority dateDec 3, 2014
Publication dateMar 2, 2021
Grant dateMar 2, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention provides a banknote processing machine having a power control electronics that comprises: —a low voltage monitor constructed to detect a lowering of a voltage of the power delivered by the power source below a minimum voltage; and —a power failure control circuit constructed to, in the case that a lowering of said voltage below said minimum voltage occurs, discontinue supply of power to a first group of said elements and to continue supply of power to a second group of said elements.

First claim

Opening claim text (preview).

I claim: 1. A banknote processing machine comprising the following elements: a plurality of electromechanical parts to control a transport of banknotes along a transport path through the banknote processing machine; a plurality of sensors located along the transport path to capture features of banknotes transported along the transport path while passing by the plurality of sensors; a computer system including one or more processors and a storage device having executable instructions stored thereon that when executed by the one or more processors configure the computer system to control transport of the banknotes along the transport path by the plurality of electromechanical parts, said computer system being configured to generate deposit data based on banknotes that have been transported along the transport path, said computer system including a deposit data memory and said computer system being configured to store generated deposit data to the deposit data memory, said executable instructions including application software; an interface between the banknote processing machine and an operator thereof or a network; a power control configured to supply power delivered by a power source to the plurality of electromechanical parts, the plurality of sensors, the computer system, and the interface; wherein the power control includes a low voltage monitor that detects a lowering of a voltage of the power delivered by the power source below a minimum voltage and to provide a low power signal; and a power control circuit that receives an output from the low voltage monitor, wherein the power control circuit is configured to continue to supply power to the plurality of sensors for a first holdup period; and to the deposit data memory for at least a second holdup period which is larger than the first holdup period; and wherein, based on said output, the power control circuit discontinues, after the first holdup period, supply of power to a first group of components of said elements of the banknote processing machine and continues supply of power to a second group of components of said elements of the banknote processing machine when said voltage falls below said minimum voltage; wherein the first group of components of said elements comprises one or several of the following: at least some or all of the plurality of electromechanical parts, at least some or all of the interface, and a first subset of the plurality of sensors; wherein the second group of components of said elements includes the deposit data memory, at least one of the one or more processors responsible for the application software, and a second subset of the plurality of sensors, the second subset of the plurality of sensors being different than the first subset of the plurality of sensors; wherein the deposit data generated by the computer system includes log files that contain data related to a deposit cycle of the banknote processing machine; wherein upon an output of the low power signal from the low voltage monitor the computer system saves the log files of the deposit cycle to the deposit data memory; wherein the power control comprises a super capacitor, which is assembled in the power control such that, as long as the voltage delivered by the power source is above or not below the minimum voltage, the super capacitor is charged, and in the case that the voltage delivered by the power source is lowered below said minimum voltage, the super capacitor is isolated from the power source and discharged to ensure continuous power supply to the second group of components of said elements. 2. The banknote processing machine of claim 1 , wherein the power control circuit is configured to ensure continuous power supply to at least some elements from the second group of components of said elements, from the time of receiving the low power signal, for a duration of a power failure period which is sufficiently long for the respective element to complete a process running at the time of receiving the low power signal. 3. The banknote processing machine of claim 1 , wherein the first group of components of said elements comprises the following: at least some or all of the plurality of electromechanical parts; at least some or all of the interface; and at least some of the plurality of sensors. 4. The banknote processing machine of claim 1 , wherein the second group of components of said elements comprises at least one or several of the following: the application software and the deposit data memory. 5. The banknote processing machine of claim 1 , wherein the second group of components of said elements comprises all of the plurality of sensors. 6. The banknote processing machine according to claim 1 , wherein the first holdup period is from about 300 to about 1000 milliseconds. 7. The banknote processing machine according to claim 1 , wherein the second holdup period is from about 4 to about 10 seconds from the time the low power signal goes on. 8. The banknote processing machine according to claim 1 , wherein the power control circuit is configured to continue to supply power to the deposit data memory for the second holdup period which is from about 5 to about 6 seconds from the time the low power signal goes on. 9. The banknote processing machine of claim 1 , wherein the first group of components of said elements includes at least some or all of the plurality of electromechanical parts. 10. The banknote processing machine of claim 1 , wherein the first group of components of said elements includes at least some or all of the interface. 11. The banknote processing machine of claim 1 , wherein the first group of components of said elements includes at least some of the plurality of sensors. 12. The banknote processing machine according to claim 1 , wherein the power control circuit is configured to continue to supply power to the plurality of sensors for the first holdup period of about 500 milliseconds.

Assignees

Inventors

Classifications

  • G07D11/40Primary

    Device architecture, e.g. modular construction · CPC title

  • Paper-money handling devices · CPC title

  • Record keeping (transaction aspects G07F19/00) · CPC title

  • G07D11/26Primary

    Servicing, repairing or coping with irregularities, e.g. power failure or vandalism · CPC title

  • for monitoring or indicating operating conditions; for detecting malfunctions · CPC title

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What does patent US10937266B2 cover?
The invention provides a banknote processing machine having a power control electronics that comprises: —a low voltage monitor constructed to detect a lowering of a voltage of the power delivered by the power source below a minimum voltage; and —a power failure control circuit constructed to, in the case that a lowering of said voltage below said minimum voltage occurs, discontinue supply of po…
Who is the assignee on this patent?
Giesecke & Devrient Gmbh, Giesecke & Devrient Currency Technology Gmbh
What technology area does this patent fall under?
Primary CPC classification G07D11/40. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 02 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).