Phase locked loop circuit

Patent metadata

Field	Value
Publication number	US-10931287-B1
Application number	US-201916548778-A
Country	US
Kind code	B1
Filing date	Aug 22, 2019
Priority date	Aug 22, 2019
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.

First claim

The invention claimed is:

1. An apparatus comprising:
a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal; and
a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state, wherein the slew rate controller is configured to pass the first clock signal without lowering the slew rate of the first clock signal when the selection signal is in a second state, wherein the slew rate controller includes a transistor and a capacitor connected in series between a clock signal line supplied with the first clock signal and a power supply line, and
wherein the transistor is brought into an ON state when the selection signal is in the first state, and brought into an OFF state when the selection signal is in the second state.

2. The apparatus of claim 1 , wherein the phase frequency detector is configured to decrease an operation current when the selection signal is in the first state.

3. An apparatus comprising:
a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal;
a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state, wherein the slew rate controller is configured to pass the first clock signal without lowering the slew rate of the first clock signal when the selection signal is in a second state;
an oscillator circuit configured to generate a third clock signal based on the phase detection signal;
a clock divider configured to generate the second clock signal by dividing the third clock signal when the selection signal is in the first state; and
a switch circuit configured to supply the second clock signal to the phase frequency detector when the selection signal is in the first state.

4. The apparatus of claim 3 , wherein the switch circuit is configured to supply the third clock signal to the phase frequency detector as the second clock signal when the selection signal is in the second state.

5. An apparatus comprising:
a phase frequency detector configured to compare a phase difference between a first clock signal and a second clock signal to generate a phase detection signal;
a clock generation circuit configured to generate the second clock signal, of which a frequency is controlled to be equal to a frequency of the first clock signal, based on the phase detection signal; and
a slew rate controller configured to control a slew rate of the first clock signal based on the frequency of the first clock signal.

6. The apparatus of claim 5 , wherein the clock generation circuit includes:
an oscillator circuit configured to generate a third clock signal based on the phase detection signal;
a clock divider configured to generate a fourth clock signal by dividing the third clock signal when the frequency of the first clock is smaller than a frequency of the third clock signal; and
a switch circuit configured to transfer the fourth clock signal as the second clock signal to the phase frequency detector when the frequency of the first clock is smaller than a frequency of the third clock signal.

7. The apparatus of claim 6 , wherein a slew rate of the fourth clock signal differ from a slew rate of the third clock signal.

8. The apparatus of claim 6 , wherein the switch circuit is configured to transfer the third clock signal as the second clock signal to the phase frequency detector when the frequency of the first clock is substantially the same as the frequency of the third clock signal.

9. The apparatus of claim 8 , wherein the slew rate controller is configured to control the slew rate of the first clock signal such that the slew rate of the first clock signal when the switch circuit outputs the fourth clock signal as the second clock signal differs from the slew rate of the first clock signal when the switch circuit outputs the third clock signal as the second clock signal.

10. The apparatus of claim 9 , wherein the slew rate of the fourth clock signal is lower than the slew rate of the third clock signal.

11. The apparatus of claim 10 , wherein the slew rate of the first clock signal when the switch circuit outputs the fourth clock signal as the second clock signal is lower than the slew rate of the first clock signal when the switch circuit outputs the third clock signal as the second clock signal.

12. The apparatus of claim 11 , wherein the slew rate of the fourth clock signal is substantially the same as the slew rate of the first clock signal when the switch circuit outputs the fourth clock signal as the second clock signal.

13. The apparatus of claim 8 ,
wherein the slew rate controller includes a transistor and a capacitor connected in series between a clock signal line supplied with the first clock signal and a power supply line, and
wherein the transistor is brought into an ON state when the switch circuit outputs the fourth clock signal as the second clock signal, and brought into an OFF state when the switch circuit outputs the third clock signal as the second clock signal.

14. The apparatus of claim 6 , wherein the phase frequency detector is configured to decrease an operation current when the switch circuit outputs the third clock signal as the second clock signal.

15. The apparatus of claim 5 , wherein the first clock signal is externally supplied.

16. An apparatus comprising:
a phase frequency detector configured to compare a phase difference between first and second clock signals; and
a current control circuit configured to control an operation current of the phase frequency detector based on a slew rate of the first and second clock signals, wherein the current control circuit comprises a first transistor, a second transistor, and a third transistor, wherein the first transistor is configured to provide the operation current, wherein a current the same as the operation current or a current proportional to the operation current flows through the second transistor and third transistor, and wherein a frequency of at least one of the first and second clock signals is adjusted based on the current flowing through the second transistor and the third transistor.

17. The apparatus of claim 16 , wherein the current control circuit is configured to control the operation current such that an amount of the operation current is a first amount when the slew rate of the first and second clock signals is a first rate, and that an amount of the operation current is a second amount lower than the first amount when the slew rate of the first and second clock signals is a second rate lower than the first rate.

18. The apparatus of claim 17 ,
wherein each of the first and second clock signals has a first frequency when the slew rate of the first and second clock signals is the first rate, and
wherein each of the first and second clock signals has a second frequency lower than the first frequency when the slew rate of the first and second clock signals is the second rate.

Assignees

• Micron Technology Inc

Inventors

• Takai Yasuhiro
• Brox Martin
• Balakrishnan Mani
• Kuzmenka Maksim

Classifications

• H03L7/10

  for assuring initial synchronisation or for broadening the capture range · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title