Bi-directional snapback ESD protection circuit

Patent metadata

Field	Value
Publication number	US-10930644-B2
Application number	US-201816195681-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Mar 4, 2016
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

First claim

What is claimed is:

1. An ESD protection circuit coupled between a first node and a second node for protecting an integrated circuit from ESD damage, wherein at the first node exits a first voltage, and at the second node exits a second voltage, the ESD protection circuit comprising:
a discharging transistor having a drain, a gate, a source and a body, wherein the drain is coupled to the first node, the source is coupled to the second node, the gate is coupled to a driving voltage; and
a body snatching circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first node, the second input terminal is coupled to the second node, and the output terminal is coupled to the body, and wherein the body snatching circuit is configured to output a lower one of the first voltage and the second voltage at the output terminal.

2. The ESD protection circuit of claim 1 , wherein the discharging transistor comprises a Metal-Oxide-Semiconductor transistor.

3. The ESD protection circuit of claim 1 , wherein the discharging transistor comprises an N-type transistor.

4. The ESD protection circuit of claim 1 , wherein the discharging transistor is configured to output an output signal of the integrated circuit at the drain.

5. The ESD protection circuit of claim 4 , wherein the driving voltage is provided by a driving stage of the integrated circuit, and wherein the driving stage is configured to drive the discharging transistor to output the output signal.

6. The ESD protection circuit of claim 1 , wherein the first node is an output pad and the second node is a ground pad.

7. The ESD protection circuit of claim 1 , wherein the body snatching circuit comprises:
a first transistor having a drain, a source, a gate and a body, wherein the drain of the first transistor is coupled to the first node, the gate of the first transistor is coupled to the second node, and the source of the first transistor and the body of the first transistor are coupled to the body of the discharging transistor; and
a second transistor having a drain, a source, a gate and a body, wherein the drain of the second transistor is coupled to the second node, the gate of the second transistor is coupled to the first node, and the source of the second transistor and the body of the second transistor are coupled to the body of the discharging transistor.

8. The ESD protection circuit of claim 7 , wherein the first transistor and the second transistor respectively comprise an NMOS.

9. A circuitry, comprising:
an ESD protection circuit coupled between a first node and a second node, wherein at the first node exits a first voltage, and at the second node exits a second voltage, and wherein the ESD protection circuit comprises:
a discharging transistor having a drain, a gate, a source and a body, wherein the drain is coupled to the first node, the source is coupled to the second node, the gate is coupled to a driving voltage; and
a body snatching circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first node, the second input terminal is coupled to the second node, and the output terminal is coupled to the body, and wherein the body snatching circuit is configured to output a lower one of the first voltage and the second voltage at the output terminal; and

an integrated circuit coupled between the first node and the second node.

10. The circuitry of claim 9 , wherein the discharging transistor comprises a Metal-Oxide-Semiconductor transistor.

11. The circuitry of claim 9 , wherein the discharging transistor comprises an N-type transistor.

12. The circuitry of claim 9 , wherein the discharging transistor is configured to output an output signal of the integrated circuit at the drain.

13. The circuitry of claim 12 , wherein the driving voltage is provided by a driving stage of the integrated circuit, and wherein the driving stage is configured to drive the discharging transistor to output the output signal.

14. The circuitry of claim 9 , wherein the first node is an output pad and the second node is a ground pad.

15. The circuitry of claim 9 , wherein the body snatching circuit comprises:
a first transistor having a drain, a source, a gate and a body, wherein the drain of the first transistor is coupled to the first node, the gate of the first transistor is coupled to the second node, and the source of the first transistor and the body of the first transistor are coupled to the body of the discharging transistor; and
a second transistor having a drain, a source, a gate and a body, wherein the drain of the second transistor is coupled to the second node, the gate of the second transistor is coupled to the first node, and the source of the second transistor and the body of the second transistor are coupled to the body of the discharging transistor.

16. The circuitry of claim 15 , wherein the first transistor and the second transistor respectively comprise an NMOS.

Assignees

• Monolithic Power Systems Inc

Inventors

• Braun Eric

Classifications

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D89/815 Primary

  involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title