Multilayer wiring substrate, display unit, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-10930594-B2
Application number	US-201515531186-A
Country	US
Kind code	B2
Filing date	Nov 11, 2015
Priority date	Dec 5, 2014
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment.

First claim

The invention claimed is:

1. A multilayer wiring substrate comprising:
a substrate; and
a first wire and a second wire that are provided on the substrate such that the first wire creates optical inspection noise under the second wire in an optical inspection of the second wire, with an insulating layer having a light transmitting property in between,
wherein the first wire is optically differentiated from the second wire with the first wire receiving a different surface treatment than the second wire,
wherein the second wire receives no surface treatment and a pitch width of the first wire is different than the pitch width of the second wire, wherein the first wire is provided on lower layer side of the insulating layer, and the second wire is provided on upper layer side of the insulating layer,
wherein the first wire is coated with a metal material whose reflection factor is lower than a reflection factor of a material of the first wire, the metal material differing from the material of the first wire, and
wherein the metal material has a lower capacity to liberate ions than the material of the first wire under an application of an electric potential.

2. The multilayer wiring substrate according to claim 1 , wherein the different surface treatment is one of a blackening process, a blackening alternative roughing process, an etching process, and a plating process.

3. The multilayer wiring substrate according to claim 1 , wherein a width of the first wire is larger than a width of the second wire along an axis orthogonal to a direction of the optical inspection of the second wire.

4. The multilayer wiring substrate according to claim 1 , wherein the metal material has a lower capacity to liberate ions than the material of the first wire under an application of an electric potential.

5. The multilayer wiring substrate according to claim 1 , wherein the first wire and the second wire are made of materials same as each other.

6. The multilayer wiring substrate according to claim 1 , wherein each of the first wire and the second wire is made of one of copper (Cu) and nickel (Ni).

7. The multilayer wiring substrate according to claim 1 , wherein each of the first wire and the second wire is formed by plating.

8. The multilayer wiring substrate according to claim 1 , wherein the metal material is one of nickel (Ni), palladium (Pd), gold (Au), tin (Sn), tungsten (W), titanium (Ti), and an alloy thereof.

9. A display unit comprising a plurality of light emitting devices provided on the multilayer wiring substrate of claim 1 .

10. An electronic apparatus comprising a plurality of electronic devices provided on the multilayer wiring substrate of claim 1 .

11. The electronic apparatus according to claim 10 , wherein each of the electronic devices is a light receiving device.

12. The multilayer wiring substrate according to claim 1 , wherein the first wire is under the second wire in the optical inspection of the second wire.

13. The multilayer wiring substrate according to claim 12 , wherein the substrate is under the first wire in the optical inspection of the second wire.

14. The multilayer wiring substrate according to claim 12 , further comprising:
an additional wire on the substrate under the first wire in the optical inspection of the second wire.

15. The multilayer wiring substrate according to claim 14 , further comprising:
a bump between the additional wire and the first wire.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Watanabe Toshihiko

Classifications

• H10W70/695 Primary

  Organic materials · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/47 Primary

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10F77/00

  Constructional details of devices covered by this subclass (constructional details of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title