Flexible and efficient device trim support using eFuse

Patent metadata

Field	Value
Publication number	US-10930362-B2
Application number	US-202016916911-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Nov 13, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

First claim

The invention claimed is:

1. An apparatus, comprising:
a processing unit;
a memory comprising one or more flexible packets; and
one or more computer-readable storage devices storing machine instructions which,
when executed by the processing unit, cause the processing unit to:
obtain trimming instructions for a component;
look up a trimming parameter for the component in the memory; and

load the trimming parameter in a trimming register;
wherein the trimming instructions include a trimming register address and a mask and wherein when executed by the processing unit, the machine instructions cause the processing unit to load the trimming parameter in the trimming register indicated by the trimming register address using the mask.

2. The apparatus of claim 1 , wherein the trimming instructions further include an additional mask and wherein when executed by the processing unit, the machine instructions cause the processing unit to load the trimming parameter in the trimming register indicated by the trimming register address using the mask and the additional mask.

3. The apparatus of claim 2 , wherein the additional mask compensates for bit inversion by an interface between one or more digital components and one or more analog components in an integrated circuit.

Assignees

• Texas Instruments Inc

Inventors

• Ganesan Aravind
• Balakrishnan Jaiganesh
• Viswanathan Nagarajan
• Guntupalli Yeswanth
• Paulose Ajai
• John Mathews
• Venkataraman Jagannathan
• Shrivastava Neeraj

Classifications

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C29/822

  for read only memories · CPC title

• G11C29/027

  in fuses · CPC title

• G11C2029/0403

  during or with feedback to manufacture · CPC title

• G11C17/146

  Write once memory, i.e. allowing changing of memory content by writing additional bits · CPC title