Shift register, driving method thereof, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-10930360-B2
Application number	US-201916242472-A
Country	US
Kind code	B2
Filing date	Jan 8, 2019
Priority date	Apr 26, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

A shift register includes a first input sub-circuit configured to transfer a first input signal at a first input terminal to a first node in response to a first scan signal at a first scan terminal being active, a first level control sub-circuit configured to transfer a first power supply voltage at a first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential, and an output sub-circuit configured to transfer a first clock signal at a first clock terminal to a first output in response to the first output control node being at an active potential, and to transfer a second clock signal at a second clock terminal to a second output terminal in response to the second output control node being at an active potential.

First claim

What is claimed is:

1. A shift register, comprising:
a first scan terminal configured to receive a first scan signal;
a first input terminal configured to receive a first input signal;
a first power supply terminal configured to receive a first power supply voltage;
a second power supply terminal configured to receive a second power supply voltage;
a first clock terminal configured to receive a first clock signal;
a second clock terminal configured to receive a second clock signal;
a first output terminal configured to output a first output signal;
a second output terminal configured to output a second output signal;
a first input sub-circuit configured to transfer the first input signal at the first input terminal to a first node in response to the first scan signal at the first scan terminal being active;
a first level control sub-circuit configured to transfer the first power supply voltage at the first power supply terminal to a first output control node and a second output control node in response to the first node being at an active potential; and
an output sub-circuit configured to transfer the first clock signal at the first clock terminal to the first output terminal as the first output signal in response to the first output control node being at an active potential, and configured to transfer the second clock signal at the second clock terminal to the second output terminal as the second output signal in response to the second output control node being at an active potential.

2. The shift register of claim 1 , further comprising:
a third clock terminal configured to receive a third clock signal;
a reset terminal configured to receive a reset signal;
a second level control sub-circuit configured to transfer the third clock signal at the third clock terminal to a third node in response to the first scan signal at the first scan terminal being active;
a third level control sub-circuit configured to transfer the first power supply voltage at the first power supply terminal to a third output control node in response to the third node being at an active potential, and configured to transfer the second power supply voltage at the second power supply terminal to the third output control node in response to the first node being at an active potential; and
a reset sub-circuit configured to transfer the reset signal at the reset terminal to the third output control node in response to the reset signal at the reset terminal being active, and configured to transfer the second power supply voltage at the second power supply terminal to a second node, the first output terminal, and the second output terminal in response to the third output control node being at an active potential.

3. The shift register of claim 2 , further comprising:
a second scan terminal configured to receive a second scan signal;
a second input terminal configured to receive a second input signal;
a fourth clock terminal configured to receive a fourth clock signal;
a second input sub-circuit configured to transfer the second input signal at the second input terminal to the first node in response to the second scan signal at the second scan terminal being active; and
a fourth level control sub-circuit configured to transfer the fourth clock signal at the fourth clock terminal to the third node in response to the second scan signal at the second scan terminal being active.

4. The shift register of claim 1 ,
wherein the first input sub-circuit comprises a first transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the first input terminal, and a second electrode connected to the first node,
wherein the first level control sub-circuit comprises:
a second transistor comprising a control electrode connected to the first node, a first electrode connected to the first power supply terminal, and a second electrode connected to a second node;
a third transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the first output control node;
a fourth transistor comprising a control electrode connected to the first power supply terminal, a first electrode connected to the second node, and a second electrode connected to the second output control node;
a first capacitor comprising a first terminal connected to the second node and a second terminal connected to the second power supply terminal, and
wherein the output sub-circuit comprises:
a fifth transistor comprising a control electrode connected to the first output control node, a first electrode connected to the first clock terminal, and a second electrode connected to the first output terminal; and
a sixth transistor comprising a control electrode connected to the second output control node, a first electrode connected to the second clock terminal, and a second electrode connected to the second output terminal.

5. The shift register of claim 2 ,
wherein the second level control sub-circuit comprises a seventh transistor comprising a control electrode connected to the first scan terminal, a first electrode connected to the third clock terminal, and a second electrode connected to the third node,
wherein the third level control sub-circuit comprises:
an eighth transistor comprising a control electrode connected to the third node, a first electrode connected to the first power supply terminal, and a second electrode connected to the third output control node;
a ninth transistor comprising a control electrode connected to the first node, a first electrode connected to the third output control node, and a second electrode connected to the second power supply terminal; and
a second capacitor comprising a first terminal connected to the third output control node and a second terminal connected to the second power supply terminal, and
wherein the reset sub-circuit comprises:
a tenth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second node, and a second electrode connected to the second power supply terminal;
an eleventh transistor comprising a control electrode connected to the third output control node, a first electrode connected to the first output terminal, and a second electrode connected to the second power supply terminal;
a twelfth transistor comprising a control electrode connected to the third output control node, a first electrode connected to the second output terminal, and a second electrode connected to the second power supply terminal; and
a thirteenth transistor comprising a control electrode connected to the reset terminal, a first electrode connected to the reset terminal, and a second electrode connected to the third output control node.

6. The shift register of claim 3 ,
wherein the second input sub-circuit comprises a fourteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the first node, and a second electrode connected to the second input terminal, and
wherein the fourth level control sub-circuit comprises a fifteenth transistor comprising a control electrode connected to the second scan terminal, a first electrode connected to the third node, and a second electrode connected to the fourth clock terminal.

7. The shift register of claim 3 , further comprising:
a first control terminal configured to receive a first control signal;
a second control terminal configured to receive a second control signal;
a touch control sub-circuit configured to transfer the second power supply voltage at the second power supply terminal to the first output terminal and the second output terminal in response to

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Peng
• Fan Jun
• Liu Yusheng
• Liu Bailing
• Zhang Han
• Wang Zhen
• Qiao Yun
• Wang Zhengkui
• Cong Lele
• Li Mei

Classifications

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title