Direct host access to storage device memory space

Patent metadata

Field	Value
Publication number	US-10929309-B2
Application number	US-201715847671-A
Country	US
Kind code	B2
Filing date	Dec 19, 2017
Priority date	Dec 19, 2017
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

Apparatuses and methods of directly accessing a memory space of a storage device by a host are provided. In one embodiment, a method of driverless access of a non-volatile memory of a non-volatile memory device by a host includes initializing a PCIe memory space mapping a portion of the non-volatile memory of the non-volatile memory device to a host memory space. The non-volatile memory is mapped through a PCIe link between the host and the non-volatile memory device. Load/store commands are sent to the PCIe memory space for driverless access. The method further includes negotiating an alignment size of the minimum transaction packet size to complete the load/store commands.

First claim

What is claimed is:

1. A method of driverless access of a non-volatile memory (NVM) of a NVM device having a NVM driver by a host having a host driver and a host dynamic random access memory (DRAM), the method comprising:
initializing a peripheral component interface express (PCIe) memory space to map a portion of the NVM of the NVM device to a host memory space through a PCIe link between the host and the NVM device by activating a base address register corresponding to a physical region of the NVM of the NVM device;
negotiating an alignment size of a minimum transaction packet size to complete load/store commands;
sending load/store commands to the PCIe memory space for driverless access of the NVM by bypassing the host DRAM, the host driver, and the NVM driver; and
sending read/write commands to the host driver of the host for driver access routed through the host DRAM, the host driver, and the NVM driver.

2. The method of claim 1 , wherein the alignment size is negotiated by:
advertising supported alignment modes by the NVM device; and
receiving a selection of an alignment mode by the host.

3. The method of claim 1 , wherein the alignment size is negotiated by:
advertising supported alignment modes by the NVM device; and
proceeding in a default alignment mode responsive to an alignment mode selection not being received within a timeout period.

4. The method of claim 1 , wherein the load/store commands are sent through the PCIe link to a controller of the NVM device.

5. The method of claim 1 , wherein the load/store commands are sent to a data-path layer of a controller to access the NVM of the NVM device.

6. The method of claim 5 , wherein the data-path layer accesses a flash translation layer to perform read/write operations in the NVM pursuant to the load/store commands.

7. The method of claim 5 , wherein the data-path layer aggregates the load/store commands in a burst operation to a NVM interface to execute read/write operations.

8. The method of claim 1 , wherein the NVM device comprises a controller.

9. The method of claim 8 , wherein the controller comprises a processor.

10. The method of claim 8 , wherein the controller comprises volatile memory.

11. The method of claim 8 , wherein the controller comprises a host interface.

12. The method of claim 8 , wherein the controller comprises a NVM interface.

13. The method of claim 8 , wherein the controller comprises the base address register.

14. A method of driver access and driverless access of a non-volatile memory (NVM) of a NVM device having a NVM driver by a host having a host driver and host dynamic random access memory (DRAM), the method comprising:
initializing a peripheral component interface express (PCIe) memory space to map a portion of the NVM of the NVM device to a host memory space through a PCIe link between the host and the NVM device by activating a base address register corresponding to a physical region of the NVM of the NVM device;
initializing a PCIe configuration space with a configuration information of the device;
sending load/store commands to the PCIe memory space for driverless access bypassing the host DRAM, the host driver, and the NVM driver; and
sending read/write commands to the host driver of the host for driver access routed through the host DRAM, the host driver, and the NVM driver utilizing the configuration information of the device.

15. The method of claim 14 , wherein the host driver sends read/write commands to the NVM driver of the device.

16. The method of claim 14 , further comprising executing in parallel the load/store commands and the read/write commands in different portions of the NVM.

17. The method of claim 14 , further comprising sequentially executing the load/store commands and the read/write commands in overlapping portions of the NVM.

18. The method of claim 14 , further comprising re-initializing the PCIe memory space for driverless access to the NVM device by mapping another portion of the NVM to logical addresses of the host.

19. The method of claim 18 , wherein the PCIe memory space is re-initialized to change a mapped size of the NVM for driverless access.

20. The method of claim 14 , wherein the controller comprises an anomaly detector module.

21. The method of claim 20 , wherein the anomaly detector module comprises a parameter tracking module.

22. The method of claim 20 , wherein the anomaly detector module comprises a normal-pattern-fitting module.

23. The method of claim 20 , wherein the anomaly detector module comprises an anomaly determination module.

24. The method of claim 20 , wherein the anomaly detector module comprises a countermeasure module.

25. A non-volatile memory (NVM) device, comprising, a link interface configured to be linked to a host having a host driver and a host dynamic random access memory (DRAM);
a NVM; and
a controller coupled to the NVM and having a NVM driver, wherein the controller is configured to:
receive a driverless access command;
route the driverless access command to bypass the host DRAM, the host driver, and the NVM driver;
receive a driver access command from the host driver; and
route the driver access command through the host DRAM, the host driver, and the NVM driver, wherein the host dynamically activates and deactivates one or more base address registers to provide driverless access for the driverless access command.

26. The device of claim 25 , wherein the NVM driver comprises a NVM Express interface protocol layer.

27. The device of claim 25 , wherein the link interface is a peripheral component interface express (PCIe) link interface.

28. The NVM device of claim 25 , wherein the controller further comprises read only memory (ROM).

29. A non-volatile memory (NVM) device, comprising,
means to link a host having a host driver and a host dynamic random access memory (DRAM);
a NVM; and
a controller coupled to the NVM and having a NVM driver, wherein the controller is configured to:
receive a driverless access command;
route the driverless access command to bypass the host DRAM, the host driver, and the NVM driver;
receive a driver access command from the host driver; and
route the driver access command through the host DRAM, the host driver, and the NVM driver, wherein the host dynamically activates and deactivates one or more base address registers to provide driverless access for the driverless access command.

Assignees

• Western Digital Tech Inc

Inventors

• Benisty Shay
• Marcu Alon
• Navon Ariel

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F12/023

  Free address space management · CPC title

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title