Storing address of spare in failed memory location

Patent metadata

Field	Value
Publication number	US-10929222-B2
Application number	US-201916405362-A
Country	US
Kind code	B2
Filing date	May 7, 2019
Priority date	Sep 29, 2015
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

First claim

What is claimed is:

1. A system comprising:
a memory; and
an integrated circuit (IC) coupled to the memory, wherein the integrated circuit is configured to access the memory in response to a plurality of memory operations, and in addition to memory accesses in response to the plurality of memory operations, the integrated circuit is configured to perform a first write in conjunction with a first memory operation of the plurality of memory operations that accesses a first entry in the memory, wherein performing the first write includes selecting a second entry in the memory, reading a content of the second entry, and writing the content back to the second entry, and wherein the integrated circuit is configured to select the second entry as a neighboring entry to the first entry.

2. The system as recited in claim 1 further comprising periodically performing the first write in conjunction with selected memory operations of the plurality of memory operations.

3. The system as recited in claim 2 wherein the plurality of memory operations comprises a plurality of write memory operations, and wherein periodically performing the first write comprises performing the first write once every P write memory operations, where P is an integer.

4. The system as recited in claim 1 wherein the plurality of memory operations comprises a plurality of read memory operations, and wherein the integrated circuit is further configured to selectively write data read in response to the plurality of read memory operations back to entries in the memory from which the data was read.

5. The system as recited in claim 4 wherein the integrated circuit is configured to write the data back one every Q read operations, where Q is an integer.

6. The system as recited in claim 5 wherein the data written back to the memory is error-corrected in response to one or more errors detected when the data is read.

7. The system as recited in claim 1 wherein the first entry is addressed using a first address, and wherein a second address of the neighboring entry is determined from the first address.

8. The system as recited in claim 7 wherein the second address is determined by incrementing the first address.

9. The system as recited in claim 1 wherein the neighboring entry is physically located near the first entry in the memory.

10. An integrated circuit comprising:
one or more agents configured to generate memory operations; and
a memory control circuit coupled to the one or more agents and configured to access a memory in response to the memory operations, and wherein the memory operations include write memory operations, and wherein the memory control circuit is configured to selectively generate additional write memory operations corresponding to a subset of the write memory operations, wherein a first write memory operation of the additional write memory operations generated for a second write memory operation of the subset of write memory operations accesses a neighboring entry in the memory to a first entry written in response to the second write memory operation.

11. The integrated circuit as recited in claim 10 wherein the memory control circuit is configured to read data from the neighboring entry and write the data back to the neighboring entry in response to the first write memory operation.

12. The integrated circuit as recited in claim 10 wherein the write memory operations are performed over time, and wherein the subset of the write memory operations are separated from each other in the performance of the write memory operations over time.

13. The integrated circuit as recited in claim 12 wherein the subset of the write memory operations comprises one write memory operation out of every P write memory operations, where P is an integer.

14. The integrated circuit as recited in claim 10 wherein the first entry is addressed using a first address, and wherein a second address of the neighboring entry is determined from the first address.

15. The integrated circuit as recited in claim 14 wherein the second address is determined by incrementing the first address.

16. The integrated circuit as recited in claim 10 wherein the neighboring entry is physically located near the first entry in the memory.

17. An integrated circuit comprising:
one or more agents configured to generate memory operations; and
a memory control circuit coupled to the one or more agents and configured to access a memory in response to the memory operations, and wherein the memory operations include read memory operations, and wherein the memory control circuit is configured to selectively generate write memory operations corresponding to a subset of the read memory operations, wherein a first write memory operation generated for a first read memory operation of the subset of read memory operations writes data read in response to the first read memory operation back to an entry in the memory addressed by the first read memory operation.

18. The integrated circuit as recited in claim 17 wherein the read memory operations are performed over time, and wherein the subset of the read memory operations are separated from each other in the performance of the read memory operations over time.

19. The integrated circuit as recited in claim 18 wherein the subset of the write memory operations comprises one write memory operation out of every Q read memory operations, where Q is an integer.

20. The integrated circuit as recited in claim 17 further comprising error-correcting the data prior to writing the data back to the entry.

Assignees

• Apple Inc

Inventors

• Gulati Manu
• Biswas Sukalpa
• Wilcox Jeffrey R
• Nemati Farid

Classifications

• G11C29/70 Primary

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C2029/0409

  Online test · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F12/121

  using replacement algorithms · CPC title