Dynamic timer adjustment to improve performance and inhibit livelock conditions

Patent metadata

Field	Value
Publication number	US-10929146-B2
Application number	US-201815966805-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Apr 30, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.

First claim

We claim:

1. An electronic processing system, comprising:
a processor;
memory communicatively coupled to the processor; and
logic communicatively coupled to the processor to:
determine respective priority levels for one or more boot time events,
accumulate an amount of execution time that the one or more boot time events were processed over a sample time period,
automatically adjust a timer based on the amount of the execution time and the priority levels for the one or more boot time events,
determine a percentage of the execution time for the one or more boot time events, wherein the percentage is to correspond to the amount of the execution time for the one or more boot time events versus a total available processing time during the sample time period, and
adjust a timer interrupt rate of the timer based on a comparison of the determined percentage of the execution time and one or more thresholds.

2. The system of claim 1 , wherein the logic is further to:
determine that one or more priority levels for the one or more boot time events corresponds to one or more raised priority levels.

3. The system of claim 1 , wherein the logic is further to:
increase the timer interrupt rate if the determined percentage of the execution time is below a first threshold.

4. The system of claim 1 , wherein the logic is further to:
decrease the timer interrupt rate if the determined percentage of the execution time is above a second threshold.

5. The system of claim 1 , wherein the logic is further to:
monitor boot time events to identify events with one or more pre-determined event types;
measure execution time for event notification functions associated with the identified events; and
determine the percentage of execution time based on the measured execution time for the event notification functions over the sample time period.

6. A semiconductor package apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
determine respective priority levels for one or more boot time events,
accumulate an amount of execution time that the one or more boot time events were processed over a sample time period,
automatically adjust a timer based on the amount of the execution time and the priority levels for the one or more boot time events,
determine a percentage of the execution time for the one or more boot time events, wherein the percentage is to correspond to the amount of the execution time for the one or more boot time events versus a total available processing time during the sample time period, and
adjust a timer interrupt rate of the timer based on a comparison of the determined percentage of the execution time and one or more thresholds.

7. The apparatus of claim 6 , wherein the logic is further to:
determine that one or more priority levels for the one or more boot time events corresponds to one or more raised priority levels.

8. The apparatus of claim 6 , wherein the logic is further to:
increase the timer interrupt rate if the determined percentage of the execution time is below a first threshold.

9. The apparatus of claim 6 , wherein the logic is further to:
decrease the timer interrupt rate if the determined percentage of the execution time is above a second threshold.

10. The apparatus of claim 6 , wherein the logic is further to:
monitor boot time events to identify events with one or more pre-determined event types;
measure execution time for event notification functions associated with the identified events; and
determine the percentage of the execution time based on the measured execution time for the event notification functions over the sample time period.

11. The apparatus of claim 6 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

12. A method of managing boot events, comprising:
determining respective priority levels for one or more boot time events;
accumulating an amount of execution time that the one or more boot time events were processed over a sample time period;
automatically adjusting a timer based on the amount of the execution time and the priority levels for the one or more boot time events;
determining a percentage of the execution time for the one or more boot time events, wherein the percentage is to correspond to the amount of the execution time for the one or more boot time events versus a total available processing time during the sample time period; and
adjusting a timer interrupt rate of the timer based on a comparison of the determined percentage of the execution time and one or more thresholds.

13. The method of claim 12 , further comprising:
determining that one or more priority levels for the one or more boot time events corresponds to one or more raised priority levels.

14. The method of claim 12 , further comprising:
increasing the timer interrupt rate if the determined percentage of the execution time is below a first threshold.

15. The method of claim 12 , further comprising:
decreasing the timer interrupt rate if the determined percentage of the execution time is above a second threshold.

16. The method of claim 12 , further comprising:
monitoring boot time events to identify events with one or more pre-determined event types;
measuring execution time for event notification functions associated with the identified events; and
determining the percentage of the execution time for the event notification functions based on the measured execution time over the sample time period.

17. At least one computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
determine respective priority levels for one or more boot time events;
accumulate an amount of execution time that the one or more boot time events were processed over a sample time period;
automatically adjust a timer based on the amount of the execution time and the priority levels for the one or more boot time events;
determine a percentage of the execution time for the one or more boot time events, wherein the percentage is to correspond to the amount of the execution time for the one or more boot time events versus a total available processing time during the sample time period; and
adjust a timer interrupt rate of the timer based on a comparison of the determined percentage of the execution time and one or more thresholds.

18. The at least one computer readable storage medium of claim 17 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
determine that one or more priority levels for the one or more boot time events corresponds to one or more raised priority levels.

19. The at least one computer readable storage medium of claim 17 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
increase the timer interrupt rate if the determined percentage of the execution time is below a first threshold.

20. The at least one computer readable storage medium of claim 17 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
decrease the timer interrupt rate if the determined percenta

Assignees

• Intel Corp
• Intel Corpoartion

Inventors

• Kinney Michael
• Rothman Michael
• Zimmer Vincent
• Doran Mark

Classifications

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F9/4825

  Interrupt from clock, e.g. time of day · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title