Black matrix, color filter and method of preparing the same, display panel, and display device

US10928668B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10928668-B2
Application numberUS-201916439162-A
CountryUS
Kind codeB2
Filing dateJun 12, 2019
Priority dateOct 27, 2015
Publication dateFeb 23, 2021
Grant dateFeb 23, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A black matrix, a color filter and a method of preparing the same, a display panel, and a display device are provided, including: a plurality of first walls extending along a first direction; and a plurality of second walls extending along a second direction intersected with the plurality of first walls along the first direction at intersection regions, wherein the plurality of first walls and the plurality of second walls form a mesh-like structure with a plurality of openings. At least one of the intersection regions is to receive a main support column including a top end, and the at least one of the intersection regions to receive the main support column is widened to be larger than a dimension of the top end of the main support column to be received therein.

First claim

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What is claimed is: 1. A display panel, comprising: an array substrate including a first thin film transistor (TFT), a second thin film transistor (TFT), and a passivation layer on the first TFT and the second TFT; a color filter (CF) substrate provided oppositely to the array substrate; a liquid crystal layer provided between the array substrate and the CF substrate; a main support column provided between the CF substrate and the array substrate; and a secondary support column provided between the CF substrate and the array substrate; wherein the CF substrate comprises a base substrate, a color filter layer on the base substrate, and a black matrix on the base substrate, wherein the black matrix comprises: a plurality of first walls extending along a first direction; and a plurality of second walls extending along a second direction and intersected with the plurality of first walls along the first direction at intersection regions, wherein the plurality of first walls and the plurality of second walls form a mesh-like structure with a plurality of openings, the plurality of openings are filled with the color filter layer to form pixels, wherein at least one of the intersection regions is configured to receive the main support column including a top end, and at least another one of the intersection regions is configured to receive the secondary support column including a top end, and a dimension of the top end of the main support column is smaller than a dimension of the top end of the secondary support column, the main support column is provided between a position on the passivation layer corresponding to the first TFT and the at least one of the intersection regions, and the secondary support column is provided between another position of the passivation layer corresponding to the second TFT and the at least another one of the intersection regions, wherein the at least one of the intersection regions to receive the main support column is widened to be larger than a dimension of the top end of the main support column to be received therein, and the widened intersection region has an oval-like shape or a pentagon-like shape, and a distance d 1 between a boundary of the top end of the main support column and a boundary of the widened intersection region in the at least one of the intersection regions is in a range of about 0.5 μm to about 1 μm, and a press gap is about 0.1% to 0.8%. 2. The display panel according to claim 1 , wherein the array substrate further comprises a gate electrode; a gate insulating layer; an active layer; a first electrode layer; source-drain electrodes; and a second electrode provided thereon. 3. The display panel according to claim 1 , wherein the first TFT is one of a switch TFT or a drive TFT, and the second TFT is another one of the switch TFT or the drive TFT. 4. The display panel according to claim 1 , wherein the first TFT comprises a first active layer, the second TFT comprises a second active layer, the top end of the main support column is provided on the first active layer of the first TFT, and the top end of the secondary support column is provided on the second active layer. 5. The display panel according to claim 1 , wherein an orthographic projection of each of the main support column and the secondary support column on the array substrate falls in that of a corresponding intersection region on the array substrate. 6. A display device, comprising a display panel, wherein the display panel comprises: an array substrate including a first thin film transistor (TFT), a second thin film transistor (TFT), and a passivation layer on the first TFT and the second TFT; a color filter (CF) substrate provided oppositely to the array substrate; a liquid crystal layer provided between the array substrate and the CF substrate; a main support column provided between the CF substrate and the array substrate; and a secondary support column provided between the CF substrate and the array substrate, wherein the CF substrate comprises a base substrate, color filter layer on the base substrate, and a black matrix on the base substrate, wherein the black matrix comprises: a plurality of first walls extending along a first direction; and a plurality of second walls extending along a second direction and intersected with the plurality of first walls along the first direction at intersection regions, wherein the plurality of first walls and the plurality of second walls form a mesh-like structure with a plurality of openings, the plurality of openings are filled with the color filter layer to form pixels, wherein at least one of the intersection regions is configured to receive the main support column including a top end, and at least another one of the intersection regions is configured to receive the secondary support column including a top end, and a dimension of the top end of the main support column is smaller than a dimension of the top end of the secondary support column, the main support column is provided between a position of the passivation layer corresponding to the first TFT and the at least one of the intersection regions, and the secondary support column is provided between another position of the passivation layer corresponding to the second TFT and the at least another one of the intersection regions, wherein the at least one of the intersection regions to receive the main support column is widened to be larger than a dimension of the top end of the main support column to be received therein, and the widened intersection region has an oval-like shape or a pentagon-like shape, and a distance d 1 between a boundary of the top end of the main support column and a boundary of the widened intersection region in the at least one of the intersection regions is in a range of about 0.5 μm to about 1 μm, and a press gap is about 0.1% to 0.8%. 7. The display device according to claim 6 , wherein the first TFT comprises a first active layer, the second TFT comprises a second active layer, the top end of the main support column is provided on the first active layer of the first TFT, and the top end of the secondary support column is provided on the second active layer. 8. The display device according to claim 6 , wherein the array substrate further comprises a gate electrode; a gate insulating layer; an active layer; a first electrode layer; source-drain electrodes; and a second electrode provided thereon. 9. The display device according to claim 6 , wherein the first TFT is one of a switch TFT or a drive TFT, and the second TFT is another one of the switch TFT or the drive TFT. 10. The display device according to claim 6 , wherein an orthographic projection of each of the main support column and the secondary support column on the array substrate falls in that of a corresponding intersection region on the array substrate. 11. A method of preparing a display panel, wherein the display panel comprises: an array substrate including a first thin film transistor (TFT), a second thin film transistor (TFT), and a passivation layer on the first TFT and the second TFT; a color filter (CF) substrate provided oppositely to the array substrate; a liquid crystal layer provided between the array substrate and the CF substrate; a main support column provided between the CF substrate and the array; and a secondary support column provided between the CF substrate and the array substrate, wherein the CF substrate comprises a base substrate, a color filter layer on the base substrate, and a black matrix on the base substrate, wherein the black matrix comprises: a plurality of first walls extending along a first direction; and a plurality of second walls extending along a second direction

Assignees

Inventors

Classifications

  • spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

  • Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

  • Spacers having different sizes · CPC title

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Methods for their manufacture, e.g. printing, electro-deposition or photolithography · CPC title

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What does patent US10928668B2 cover?
A black matrix, a color filter and a method of preparing the same, a display panel, and a display device are provided, including: a plurality of first walls extending along a first direction; and a plurality of second walls extending along a second direction intersected with the plurality of first walls along the first direction at intersection regions, wherein the plurality of first walls and …
Who is the assignee on this patent?
Beijing Boe Optoelectronics Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/133512. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 23 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).