Transmitter with fully re-assignable segments for reconfigurable FFE taps

Patent metadata

Field	Value
Publication number	US-10924310-B2
Application number	US-201916277392-A
Country	US
Kind code	B2
Filing date	Feb 15, 2019
Priority date	Sep 10, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

First claim

What is claimed is:

1. A circuitry comprising:
a delay generator operable to:
receive a data stream;
generate a staggered data stream based on the received data stream, wherein data among the staggered data stream are positioned at staggered unit intervals;
a plurality of segments coupled to the delay generator, a segment provides:
a pulse generator operable to:
receive the staggered data stream from the delay generator;
perform AND operations on the staggered data stream with respective pair of clock signals of different phases to carve the staggered data stream into one unit interval pulses at a specific unit interval, wherein the specific unit interval indicates an assignment of a corresponding segment of the plurality of segments as one of a feed forward equalization (FFE) pre tap, a FFE main tap, and a FFE post tap;
a phase selector coupled to the pulse generator, the phase selector operable to define the specific unit interval; and
an output circuit operable to output the one unit interval pulses carved from the staggered data stream in accordance with the specific unit interval.

2. The circuitry of claim 1 , wherein the delay generator and the plurality of segments are parts of a slice, the slice being among a plurality of slices of a data transmission system, and wherein:
the received data stream is a portion of an input data stream received by the data transmission system; and
the one unit interval pulses outputted from the plurality of segments are combined with one unit interval pulses outputted from other slices among the plurality of slices to form a reproduced version of the input data stream.

3. The circuitry of claim 1 , wherein the pulse generator comprises a plurality of AND gates operable to perform the AND operations, and, wherein the pair of clock signals define the specific unit interval.

4. The circuitry of claim 3 , wherein the phase selector is operable to select the pair of clock signals.

5. The circuitry of claim 1 , wherein the phase selector is operable to:
receive a plurality of incoming clock signals;
receive a selection signal; and
output the respective pair of clock signals based on the selection signal, wherein the pair of clock signals define the specific unit interval.

6. The circuitry of claim 1 , wherein the pulse generator of the segment is operable to receive a signal to change a polarity of the staggered data stream.

7. The circuitry of claim 1 , wherein:
a first number of segments among the plurality of segments is assigned as the FFE pre tap corresponding to at least one pre-cursor of the outputted one unit interval pulses, and a number of segments assigned to the FFE pre tap corresponds to a coarse weight setting of a corresponding pre-cursor of the outputted one unit interval pulses;
a second number of segments among the plurality of segments is assigned as the FFE main tap corresponding to a main-cursor of the outputted one unit interval pulses, and the second number corresponds to a coarse weight setting of the main-cursor of the outputted one unit interval pulses; and
a third number of segments among the plurality of segments is assigned as the FFE post tap corresponding to at least one post-cursor of the outputted one unit interval pulses, and a number of segments assigned to the FFE post tap corresponds to a coarse weight setting of a corresponding post-cursor of the outputted one unit interval pulses.

8. The circuitry of claim 7 , wherein the first number of segments assigned as the FFE pre tap is different from the third number of segments assigned as the FFE post tap.

9. The circuitry of claim 1 , wherein the assignment of the plurality of segments to the FFE pre tap, the FFE main tap, and the FFE post tap is reconfigurable based on changes to the specific unit interval.

10. The circuitry of claim 1 , wherein the output circuit is operable to:
receive bias voltages from a bias voltage generator coupled to the output circuit;
adjust a current of the corresponding segment based on the bias voltages to tune a tap weight of the corresponding segment; and
output the one unit interval pulses with the tuned tap weights.

11. A data transmission system comprising:
a clock generator operable to generate a plurality of clock signals of different phases;
a circuitry that provides:
a delay generator coupled to the clock generator, the delay generator operable to:
receive a data stream;
generate a staggered data stream based on the received data stream, wherein data among the staggered data stream are positioned at staggered unit intervals;

a plurality of segments coupled to the delay generator, a segment provides:
a pulse generator operable to:
receive the staggered data stream from the delay generator;
perform AND operations on the staggered data stream with a selected pair of clock signals among the plurality of clock signals to carve the staggered data stream into one unit interval pulses at a specific unit interval, wherein the specific unit interval indicates an assignment of a corresponding segment of the plurality of segments as one of a feed forward equalization (FFE) pre tap, a FFE main tap, and a FFE post tap;

a phase selector coupled to the clock generator and the pulse generator, the phase selector is operable to select a pair of clock signals generated by the clock generator to define the specific unit interval; and
an output circuit operable to output the one unit interval pulses carved from the staggered data stream in accordance with the specific unit interval.

12. The data transmission system of claim 11 , further comprises a plurality of slices, wherein:
the circuitry is part of a slice among the plurality of slices;
the received data stream is a portion of an input data stream received by the data transmission system; and
the one unit interval pulses outputted from the plurality of segments of the circuitry are combined with one unit interval pulses outputted from other slices among the plurality of slices to form a reproduced version of the input data stream.

13. The data transmission system of claim 11 , wherein the phase selector is operable to:
receive a plurality of incoming clock signals;
receive a selection signal; and
output the pair of selected clock signals based on the selection signal, wherein the pair of clock signals define the specific unit interval.

14. The data transmission system of claim 11 , wherein the pulse generator of the segment is operable to receive a signal to change a polarity of the staggered data stream.

15. The data transmission system of claim 11 , wherein:
a first number of segments among the plurality of segments is assigned as the FFE pre tap corresponding to at least one pre-cursor of the outputted one unit interval pulses, and a number of segments assigned to the FFE pre tap corresponds to a coarse weight setting of a corresponding pre-cursor of the outputted one unit interval pulses;
a second number of segments among the plurality of segments is assigned as the FFE main tap corresponding to a main-cursor of the outputted one unit interval pulses, and the second number corresponds to a coarse weight setting of the main-cursor of the outputted one unit interval pulses; and
a third number of segments among the plurality of segments is assigned as the FFE post tap corresponding to at least one post-cursor of the outputted one unit interval pulses, and a number of segments assigned to the FFE post tap corresponds to a coarse weight setting of a corresponding post-cursor of the outputted one unit interval pulses.

16. The data transmission syste

Assignees

• IBM

Inventors

• Toprak-Deniz Zeynep
• Bulzacchelli John F
• Ainspan Herschel A
• Proesel Jonathan E
• Meghelli Mounir

Classifications

• H04L27/0002

  analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line (duplex arrangements H04L5/143) · CPC title

• H04L25/03133

  with a non-recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L25/4917

  using multilevel codes · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title