Low-loss silicon on insulator based dielectric microstrip line

Patent metadata

Field	Value
Publication number	US-10923790-B2
Application number	US-201715437133-A
Country	US
Kind code	B2
Filing date	Feb 20, 2017
Priority date	Feb 20, 2017
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Systems and methods which provide low-loss dielectric microstrip line (DML) circuits for use with respect to signals in the terahertz frequency range are described. Low-loss DML integrated circuits of embodiments, such as may comprise DML transmission lines, DML couplers, DML crossovers, etc., may be based on silicon technology and are adapted for signal frequencies in the range of 750-925 GHz. A DML circuit implementation may be comprised of silicon on insulator based DML structure having a silicon dioxide (SiO2) insulation layer as the middle layer of the DML, wherein the device layer (HR—Si) and the handle layer (HR—Si) are the top and bottom layers of the DML. A high-precision fabrication process for the SOI wafer, wherein the height of the dielectric microstrip lines can be accurately controlled, may be utilized to fabricate DML circuits of embodiments. A non-contact measurement technology may be used to test the DML circuits of embodiments.

First claim

What is claimed is:

1. A silicon on insulator (SOI) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the DML circuit comprising:
a silicon dioxide (SiO 2 ) insulation layer of the SOI providing a middle layer of the DML circuit, wherein the middle SiO2 layer of the DML circuit has a thickness t;
a high-resistivity silicon (HR—Si) layer providing a top layer of the DML circuit, wherein the top HR—Si layer of the DML circuit has height h 1 , and wherein a DML structure formed in the top HR—Si layer of the DML circuit has width w; and
a HR—Si layer providing a bottom layer of the DML, wherein the bottom HR—Si layer of the DML circuit has height h 2 , and wherein values for parameters h 1 , h 2 , and w are selected for a particular value of parameter t and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a crossover circuit having two mutually perpendicular DML structures in a same plane.

2. The SOI based DML circuit of claim 1 , wherein the values for parameters w, h 1 , and h 2 are selected to achieve a smallest attenuation constant of DML for the particular value of parameter t.

3. The SOI based DML circuit of claim 1 , wherein the particular value of parameter t is 2 μm, the selected values for parameters w, h 1 , and h 2 are 150 μm, 65 μm, and 65 μm respectively.

4. The SOI based DML circuit of claim 1 , wherein the top HR—Si layer of the DML circuit comprises a device layer and the bottom HR—Si layer of the DML circuit comprises a handle layer.

5. The SOI based DML circuit of claim 1 , wherein each of the two mutually perpendicular DML structures comprise DMLs with dimensions w=150 μm, h 1 =65 μm, h 2=65 μm and t=2 μm.

6. The SOI based DML circuit of claim 1 , wherein the crossover circuit provides at least 24 dB isolation between inputs of the mutually perpendicular DML structures.

7. The SOI based DML circuit of claim 6 , wherein the isolation between inputs of the mutually perpendicular DML structures is 25.45±5.54 dB.

8. A silicon on insulator (SOI) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the DML circuit comprising:
a silicon dioxide (SiO 2 ) insulation layer of the SOI providing a middle layer of the DML circuit, wherein the middle SiO 2 layer of the DML circuit has a thickness t;
a high-resistivity silicon (HR—Si) layer providing a top layer of the DML circuit, wherein the top HR—Si layer of the DML circuit has height h l , and wherein a DML structure formed in the top HR—Si layer of the DML circuit has width w; and
an HR—Si layer providing a bottom layer of the DML, wherein the bottom HR—Si layer of the DML circuit has height h 2 , and wherein values for parameters h l , h 2 , and w are selected for a particular value of parameter t and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a coupler circuit having two DML structures having a 45° intersection angle in a same plane.

9. The SOI based DML circuit of claim 8 , wherein each of the intersecting DML structures comprise DMLs with dimensions w=150 μm, h 1 =65 μm, h 2=65 μm and t=2 μm.

10. The SOI based DML circuit of claim 8 , wherein the coupler circuit provides a coupler factor of at least −10 dB.

11. The SOI based DML circuit of claim 10 , wherein the coupler factor is −13.22±3.23 dB.

12. A silicon on insulator (SOI) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the DML circuit comprising:
a silicon dioxide (SiO 2 ) insulation layer of the SOI providing a middle layer of the DML circuit, wherein the middle SiO 2 layer of the DML circuit has a thickness t;
a high-resistivity silicon (HR—Si) layer providing a top layer of the DML circuit, wherein the top HR—Si layer of the DML circuit has height h 1 , and wherein a DML structure formed in the top HR—Si layer of the DML circuit has width w; and
an HR—Si layer providing a bottom layer of the DML, wherein the bottom HR—Si layer of the DML circuit has height h 2 , and wherein values for parameters h 1 , h 2 , and w are selected for a particular value of parameter t and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a H-plane dielectric horn antenna.

13. The SOI based DML circuit of claim 12 , wherein the H-plane dielectric horn antenna configures the DML circuit for operation with a non-contact measurement system.

14. The SOI based DML circuit of claim 12 , wherein the H-plane dielectric horn antenna comprises a dielectric extension area of length g, wherein a value of parameter g is selected to match the H-plane dielectric horn antenna to free space.

15. A silicon on insulator (SOT) based dielectric microstrip line (DML) circuit configured for operation with signals in a range of 750-925 GHz, the SOT based DML circuit comprising:
a first layer having height h 1 and width w, wherein w is at least 150 μm and h 1 , is 65 μm or less;
a second layer having thickness t, wherein t is at least 2 μm; and
a third layer having height h 2 , wherein t is at least 2 μm, w is at least 150 μm, h 1 , is 65 μm or less, and h 2 is 65 μm or less and configure the DML circuit for the operation with the signals in the range of 750-925 GHz, wherein the DML circuit comprises a crossover circuit having two mutually perpendicular DML structures in a same plane or the DML circuit comprises a coupler circuit having two DML structures having a 45° intersection angle in a same plane.

16. The SOI based DML circuit of claim 15 , wherein the first and third layers comprise a high-resistivity silicon (HR—Si) layers and the second layer comprises a silicon dioxide (SiO 2 ) insulation layer.

17. The SOI based DML circuit of claim 15 , wherein the values for parameters w, h 1 , and h 2 are selected to achieve a smallest attenuation constant of DML for the value of the thickness parameter t.

Assignees

• Univ City Hong Kong

Inventors

• Xue Quan
• Zhu Hao-Tian

Classifications

• H10W44/248

  for antennas · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/01

  Manufacture or treatment · CPC title