Photodiode, photodiode array, and solid-state imaging device

Patent metadata

Field	Value
Publication number	US-10923614-B2
Application number	US-201515328648-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Jul 25, 2014
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region includes: a p− type semiconductor layer having interfaces; an n+ type semiconductor region located inside the p− type semiconductor layer and in contact with the interface; an n+ type semiconductor region located inside the p− type semiconductor layer and connected to the n+ type semiconductor region; and a p type semiconductor region located between the n+ type semiconductor region and the interface, wherein the n+ type semiconductor region, the n+ type semiconductor region, and the p type semiconductor region each have a higher impurity concentration than the p− type semiconductor layer, the avalanche region is a region between the n+ type semiconductor region and the p type semiconductor region inside the p− type semiconductor layer, and the n+ type semiconductor region has a smaller area than the n+ type semiconductor region in planar view.

First claim

The invention claimed is:

1. A photodiode that multiplies a charge generated by photoelectric conversion in an avalanche region, the photodiode comprising:
a semiconductor layer including silicon, the semiconductor layer having a first surface and a second surface that faces the first surface;
a first semiconductor region located inside the semiconductor layer and in contact with the first surface;
a second semiconductor region located inside the semiconductor layer and connected to the first semiconductor region; and
a third semiconductor region located between the second semiconductor region and the second surface,
wherein the semiconductor layer and the third semiconductor region are a first conductivity type,
the first semiconductor region and the second semiconductor region are a second conductivity type opposite to the first conductivity type,
the first semiconductor region, the second semiconductor region, and the third semiconductor region each have a higher impurity concentration than the semiconductor layer,
the avalanche region is a region between the second semiconductor region and the third semiconductor region inside the semiconductor layer,
the first semiconductor region has a smaller area than the second semiconductor region in planar view, and
the second semiconductor region is disposed further from the first surface than the first semiconductor region in a thickness direction of the photodiode.

2. The photodiode according to claim 1 , further comprising:
a fourth semiconductor region of the second conductivity type located inside the semiconductor layer, in contact with the first surface, and surrounding the first semiconductor region in planar view.

3. The photodiode according to claim 2 , further comprising:
a fifth semiconductor region of the first conductivity type located between the fourth semiconductor region and the first semiconductor region,
wherein the fifth semiconductor region has a higher impurity concentration than the semiconductor layer.

4. The photodiode according to claim 3 ,
wherein a region between the fifth semiconductor region and the first semiconductor region has a lower impurity concentration than the fifth semiconductor region.

5. The photodiode according to claim 2 , further comprising:
a sixth semiconductor region of the first conductivity type located between the fourth semiconductor region and the second semiconductor region,
wherein the sixth semiconductor region has a higher impurity concentration than the semiconductor layer.

6. The photodiode according to claim 5 ,
wherein the sixth semiconductor region is closer to the fourth semiconductor region than the second semiconductor region.

7. The photodiode according to claim 2 ,
wherein a first voltage of reverse bias is applied between the fourth semiconductor region and the semiconductor layer.

8. The photodiode according to claim 7 ,
wherein a second voltage of reverse bias is applied between the first semiconductor region and the semiconductor layer, and
the first voltage is higher than the second voltage.

9. The photodiode according to claim 1 ,
wherein the third semiconductor region is located inside the semiconductor layer, and has a wider area than the second semiconductor region in planar view.

10. The photodiode according to claim 1 ,
wherein the third semiconductor region is formed continuously with the semiconductor layer by crystal growth.

11. The photodiode according to claim 1 ,
wherein the second semiconductor region is formed continuously with the semiconductor layer by crystal growth.

12. The photodiode according to claim 1 ,
wherein light is applied from a side on which the second surface is located from among the first surface and the second surface.

13. The photodiode according to claim 1 ,
wherein the third semiconductor region is located inside the semiconductor layer, and is not exposed to the second surface,
the photodiode further comprises
a seventh semiconductor region of the first conductivity type located on the second surface, and
the seventh semiconductor region has a higher impurity concentration than the semiconductor layer.

14. The photodiode according to claim 1 , further comprising:
a resistor electrically connected to the first semiconductor region; and
a signal line connected to the first semiconductor region via the resistor.

15. A photodiode array comprising:
a plurality of pixels each of which has the photodiode according to claim 1 .

16. The photodiode array according to claim 15 ,
wherein the third semiconductor region is provided in common to the plurality of pixels.

17. A photodiode array comprising:
a plurality of pixels each of which has the photodiode according to claim 2 ,
wherein the fourth semiconductor region is provided in common to the plurality of pixels.

18. The photodiode array according to claim 15 ,
wherein the second semiconductor region is separated for each of the plurality of pixels by ion implanting an impurity of the first conductivity type.

19. A solid-state imaging device comprising:
the photodiode according to claim 1 ;
a charge accumulation part electrically connected to the first semiconductor region and accumulating the charge multiplied in the avalanche region; and
a detection circuit that detects the charge accumulated in the charge accumulation part.

20. The photodiode according to claim 1 , wherein the first semiconductor region and the second semiconductor region directly contact each other.

21. The photodiode according to claim 1 , wherein the second semiconductor region does not directly contact the first surface.

22. The photodiode according to claim 1 , further comprising:
a semiconductor substrate,
a first interlayer insulating film disposed on the semiconductor substrate,
a second interlayer insulating film disposed on the first interlayer insulating film,
a wiring layer disposed on the first interlayer insulating film, and
a contact plug disposed in the second interlayer insulating film,
wherein the contact plug connects the wiring layer to the first semiconductor region.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Sakata Yusuke
• Usuda Manabu
• Mori Mitsuyoshi
• Hirose Yutaka
• Kato Yoshihisa

Classifications

• H10F39/8033

  Photosensitive area · CPC title

• H10F39/1825

  Multicolour image sensors having stacked structure, e.g. NPN, NPNPN or multiple quantum well [MQW] structures · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/803 Primary

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H10F39/199

  Back-illuminated image sensors · CPC title