Camouflaged FinFET and method for producing same

Patent metadata

Field	Value
Publication number	US-10923596-B2
Application number	US-201916297516-A
Country	US
Kind code	B2
Filing date	Mar 8, 2019
Priority date	Mar 8, 2019
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.

First claim

What is claimed is:

1. A camouflaged application specific integrated circuit (ASIC), comprising:
a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, the plurality of interconnected functional logic cells comprising:
at least one camouflaged FinFET, comprising a fin having:
a source region of a first conductivity type;
a drain region of the first conductivity type;
a channel region of a second conductivity type, the channel region disposed between the source region and the drain region; and
a camouflaged fin region of the second conductivity type, the camouflaged fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.

2. The ASIC of claim 1 , further comprising a silicide layer disposed on the camouflaged fin region, the silicide layer further rendering the camouflaged FinFET in an always on condition.

3. The ASIC of claim 2 , wherein the camouflaged Fin region comprises:
a camouflaged source side fin region of the second conductivity type, disposed between the source region and the channel region; and
a camouflaged drain side fin region of the second conductivity type, disposed between the drain region and the channel region.

4. The ASIC of claim 3 , wherein:
the camouflaged source side fin region comprises:
a camouflaged source side extension region adjacent a source side of the channel region, the camouflaged source side extension region being a lightly doped region of the second conductivity type; and

the camouflaged drain side fin region comprises:
a camouflaged drain side extension region adjacent a drain side of the channel region, the camouflaged drain side extension region being a lightly doped region of the second conductivity type.

5. The ASIC of claim 4 , wherein:
the camouflaged source side fin region further comprises a camouflaged source side span region disposed between the source region and the camouflaged source side extension region; and
the camouflaged drain side fin region further comprises a camouflaged drain side span region disposed between the drain region and the camouflaged drain side extension region.

6. The ASIC of claim 5 , wherein:
the camouflaged FinFET is rendered in the always on condition by a conduction path from the source region through the silicide layer, the camouflaged source side span region, the camouflaged source side extension region, the channel region, the camouflaged drain side extension region, the camouflaged drain side span region, and the drain region.

7. The ASIC of claim 6 , wherein the first and second conductivity type are selected from the group consisting of a P conductivity type and an N conductivity type, and wherein:
the first conductivity type is one of the P conductivity type and the N conductivity type; and
the second conductivity type is the other of the P conductivity type and the N conductivity type.

8. A method of forming a camouflaged application specific integrated circuit (ASIC), comprising a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, the plurality of interconnected functional logic cells comprising at least one camouflaged FinFET, comprising:
forming a fin, the fin having:
a source region of a first conductivity type;
a drain region of the first conductivity type;
a channel region of a second conductivity type, the channel region disposed between the source region and the drain region; and
a camouflage fin region of the second conductivity type, the camouflaged fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET, the camouflaged fin region having:
a source side extension region adjacent to a source side of the channel region;
a drain side extension region adjacent to a drain side of the channel region;
a source side span region between the source region and the source side extension region; and
a drain side span region between the drain region and the drain side extension region;

forming a gate over only the channel region of the camouflaged FinFET;
doping the source side extension region and the drain side extension region according to a first conductivity type;
forming a source side gate spacer over the source side extension region and a drain side gate spacer over the drain side extension region;
implanting the source side span region and the drain side span region according to the first conductivity type;
implanting the source region and the drain region according to a second conductivity type; and
forming self-aligned silicide on the fin.

9. The method of claim 8 , wherein:
doping the source side extension region and the drain side extension region according to the first conductivity type comprises:
applying a mask exposing only the source side extension region, the drain side extension region, the source side span region and the drain side span region of the camouflaged FinFET;
implanting, with an extension implant dose, the exposed source side extension region the drain side extension region, the source side span region and the drain side span region; and

implanting the source side span region and the drain side span region according to the first conductivity type comprises:
implanting, with a source/drain implant, the exposed source side span region and the exposed drain side span region using the mask;

implanting the source region and the drain region according to the second conductivity type comprises:
applying a second mask to expose the source region and the drain region of the camouflaged FinFET; and
implanting, with the source/drain implant, the source region and the drain region.

10. The method of claim 9 , wherein the first and second conductivity type are selected from the group consisting of a P conductivity type and an N conductivity type, and wherein:
the first conductivity type is one of the P conductivity type and the N conductivity type; and
the second conductivity type is the other of the P conductivity type and the N conductivity type.

11. A camouflaged application specific integrated circuit (ASIC), formed by a process comprising process steps of:
forming a plurality of FinFETs, each FinFET concurrently formed by performing process steps comprising the steps of:
forming a fin having:
a source region;
a drain region;
a channel region; and
a camouflage region having:
a source side extension region adjacent to a source side of the channel region;
a drain side extension region adjacent to a drain side of the channel region;
a source side span region between the source region and the source side extension region; and
a drain side span region between the drain region and the drain side extension region;

forming a gate over only the channel region of the FinFET;
doping the source side extension region and the drain side extension region according to a first conductivity type;
forming a source side gate spacer over the source side extension region and a drain side gate spacer over the drain side extension region;
implanting the source side span region and the drain side span region according to the first conductivity type;
implanting the source region and the drain region according to a second conductivity type; and
forming self-aligned silicide on the fin.

12. The ASIC of claim 11 , wherein:
doping the source side extension region and the drain side extension region according to the first

Assignees

• Inside Secure
• Rambus Inc

Inventors

• Chow Lap Wai
• Wang Bryan J
• Baukus James P
• Cocchi Ronald P

Classifications

• H10W42/405

  using active circuits · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title