Integrated circuit including at least one memory cell with an antifuse device

Patent metadata

Field	Value
Publication number	US-10923484-B2
Application number	US-201916546002-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Aug 31, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

First claim

The invention claimed is:

1. An integrated circuit, including at least one memory cell, wherein the at least one memory cell comprises:
an antifuse device including a state transistor having a control gate and a second gate, wherein the second gate is configured to be floating relative to the control gate so as to confer a non-broken-down state on the antifuse device or wherein the second gate is configured to be electrically coupled to the control gate so as to confer a broken-down state on the antifuse device.

2. The integrated circuit according to claim 1 , wherein the state transistor comprises:
a first polysilicon region, wherein the control gate includes the first polysilicon region;
a second polysilicon region separated by a layer of dielectric material from the first polysilicon region, wherein the second gate includes the second polysilicon region; and
wherein the broken-down state of the antifuse device is formed by an electrical connection between the first polysilicon region and the second polysilicon region through the layer of dielectric material.

3. The integrated circuit according to claim 1 , further including an electrically conductive connecting element including a first end that is electrically coupled to the second gate and a second, free end that extends to a peripheral edge of the integrated circuit.

4. The integrated circuit according to claim 3 , including a sealing ring including metal tracks and vias extending around the entire periphery of the integrated circuit, the connecting element including a crossing part which crosses said sealing ring, the second end being located between the sealing ring and the peripheral edge.

5. The integrated circuit according to claim 2 , further comprising:
a semiconductor well having a bottom that is delimited by a buried semiconductor region;
an insulated vertical electrode in said semiconductor well extending from the upper face of the semiconductor well down to a region close to the bottom of the semiconductor well;
a heavily n-doped region providing electrical continuity between the vertical electrode and the buried semiconductor layer;
wherein said vertical electrode comprises said second polysilicon region and forms the second gate, the state transistor being a vertical transistor.

6. The integrated circuit according to claim 5 , further including an electrically conductive connecting element including a first end that is electrically coupled to the second gate and a second, free end that extends to a peripheral edge of the integrated circuit.

7. The integrated circuit according to claim 6 , including a sealing ring including metal tracks and vias extending around the entire periphery of the integrated circuit, the connecting element including a crossing part which crosses said sealing ring, the second end being located between the sealing ring and the peripheral edge.

8. The integrated circuit according to claim 1 , further comprising a memory module that includes a plurality of memory cells which are interconnected according to a matrix architecture, wherein each memory cell includes an access transistor which is coupled between the state transistor and a read line which is common to all of the memory cells.

9. The integrated circuit according to claim 8 , wherein the state transistor comprises:
a first polysilicon region, wherein the control gate includes the first polysilicon region;
a second polysilicon region separated by a layer of dielectric material from the first polysilicon region, wherein the second gate includes the second polysilicon region; and
wherein the broken-down state of the antifuse device is formed by an electrical connection between the first polysilicon region and the second polysilicon region through the layer of dielectric material.

10. The integrated circuit according to claim 9 , wherein a plurality of memory cells share one and the same second polysilicon region.

11. The integrated circuit according to claim 1 , wherein the integrated circuit is a component of a chip card.

12. The integrated circuit according to claim 1 , further comprising means for reading said at least one memory cell by:
biasing the control gate of the state transistor; and
reading a drain current of the state transistor, wherein a drain current that is below a threshold is indicative of the non-broken-down state of the antifuse device and wherein a drain current above said threshold is indicative of a broken-down state of the antifuse device.

13. A semiconductor wafer, comprising:
first zones;
second zones including cutting lines, said second zones separating first zones from each other;
wherein each first zone includes an integrated circuit, said integrated circuit including at least one memory cell, wherein the at least one memory cell comprises:
an antifuse device including a state transistor having a control gate and a second gate, wherein the second gate is configured to be floating relative to the control gate so as to confer a non-broken-down state on the antifuse device or wherein the second gate is configured to be electrically coupled to the control gate so as to confer a broken-down state on the antifuse device; and
an electrically conductive connecting element including a first end that is electrically coupled to the second gate and a second end that extends into the second zone such that the integrated circuit and the second end are located on either side of the corresponding cutting line.

14. The semiconductor wafer according to claim 13 , wherein the state transistor comprises:
a first polysilicon region, wherein the control gate includes the first polysilicon region;
a second polysilicon region separated by a layer of dielectric material from the first polysilicon region, wherein the second gate includes the second polysilicon region; and
wherein the broken-down state of the antifuse device is formed by an electrical connection between the first polysilicon region and the second polysilicon region through the layer of dielectric material.

15. The semiconductor wafer according to claim 13 , wherein each first zone includes a sealing ring including metal tracks and vias, said connecting element including a crossing part which crosses said sealing ring.

16. The semiconductor wafer according to claim 13 , further comprising:
a semiconductor well having a bottom that is delimited by a buried semiconductor region;
an insulated vertical electrode in said semiconductor well extending from the upper face of the semiconductor well down to a region close to the bottom of the semiconductor well;
a heavily n-doped region providing electrical continuity between the vertical electrode and the buried semiconductor layer;
wherein said vertical electrode comprises said second polysilicon region and forms the second gate, the state transistor being a vertical transistor.

17. A method for programming at least one memory cell, said memory cell including an antifuse device including a state transistor having a control gate and a second gate, wherein the second gate is configured to be floating relative to the control gate so as to confer a non-broken-down state on the antifuse device or wherein the second gate is configured to be electrically coupled to the control gate so as to confer a broken-down state on the antifuse device, the method comprising:
programming by either:
forming an electrical connection between the control gate and the second gate so as to have said broken-down state,
placing the second gate in the floating state so as to have said non-broken-down state.

Assignees

• St Microelectronics Rousset

Inventors

• Fornara Pascal
• Marinet Fabrice

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title