Memory arrays with bonded and shared logic circuitry

Patent metadata

Field	Value
Publication number	US-10923450-B2
Application number	US-201916437445-A
Country	US
Kind code	B2
Filing date	Jun 11, 2019
Priority date	Jun 11, 2019
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

First claim

What is claimed is:

1. An integrated circuit memory comprising:
a first memory array comprising a first plurality of memory cells;
a logic circuitry;
a first layer comprising silicon, the first layer between the first memory array and the logic circuitry;
a second memory array, wherein the logic circuitry is between the first and second memory arrays; and
a second layer comprising silicon, the second layer between the second memory array and the logic circuitry.

2. The integrated circuit memory of claim 1 , wherein each of the first and second layers has a thickness of at least 3000 angstrom.

3. The integrated circuit memory of claim 1 , wherein:
the first memory array comprises a first sidewall and an opposing second sidewall; and
the first layer extends from the first sidewall to the second sidewall.

4. The integrated circuit memory of claim 1 , wherein the first layer further comprises at least one of oxygen or nitrogen.

5. The integrated circuit memory of claim 1 , wherein the logic circuitry comprises one or more of an address decoder, a buffer, a word line driver, a bit line driver, a sense amplifier, a voltage divider, a charge pump, a digital logic block, and/or complementary metal-oxide-semiconductor (CMOS) logic.

6. The integrated circuit memory of claim 1 , wherein the logic circuitry comprises:
a first one or more transistors that operate at a first voltage in the range of 5 volts (V) to 30 V; and
a second one or more transistors that operate at a second voltage in the range of 0.9 V to 5 V.

7. The integrated circuit memory of claim 1 , wherein:
the first memory array is included in a first die that is bonded to a second die comprising the logic circuitry; and
the first layer is a bonding interface layer between the first die and the second die.

8. The integrated circuit memory of claim 1 , wherein:
the first memory array is included in a first die that is bonded to a second die comprising the logic circuitry;
the second memory array is included in a third die that is bonded to the second die;
the first layer is a first bonding interface layer between the first die and the second die;
the second layer is a second bonding interface layer between the third die and the second die; and
one or more logic components of the logic circuitry is shared by the first and second memory arrays.

9. An integrated circuit memory comprising:
a first die that includes (i) a first memory array comprising a first plurality of memory cells and (ii) a logic circuitry;
a second die that is bonded to the first die, wherein the second die includes a second memory array comprising a second plurality of memory cells;
a layer comprising silicon between the first die and the second die,
wherein the logic circuitry is between the first and second memory arrays, and one or more logic components of the logic circuitry is shared by the first and second memory arrays.

10. The integrated circuit memory of claim 1 , further comprising:
a third layer in direct contact with the first layer, the third layer comprising silicon, the second layer compositionally different from the first layer.

11. The integrated circuit memory of claim 10 , further comprising:
an interconnect structure extending through the first layer and the third layer,
wherein the interconnect structure has a first portion that extends through the third layer and a first section of the first layer, and a second portion that extends through a second section of the first layer, and
wherein the first portion of the interconnect structure is offset with respect to the second portion of the interconnect structure.

12. The integrated circuit memory of claim 1 , wherein the memory array is three-dimensional (3D) NAND flash memory array.

13. A motherboard, wherein the integrated circuit memory of claim 1 is attached to the motherboard.

14. The integrated circuit memory of claim 1 , further comprising:
a first die that includes the first memory array; and
a second die that includes the logic circuitry,
wherein the first die has a surface facing the second die, and
wherein the first layer is on substantially an entirety of the surface of the first die and/or the first layer is on substantially an entirety of the surface of the second die.

15. The integrated circuit memory of claim 1 , further comprising:
an interconnect structure to couple the first memory array and the logic circuitry, the interconnect structure extending through the first layer.

16. An integrated circuit memory comprising:
a memory array comprising a plurality of memory cells, the memory array having a first sidewall and an opposing second sidewall;
a logic circuitry having a third sidewall and an opposing fourth sidewall;
a first layer comprising silicon between the memory array and the logic circuitry, the first layer extending from the first sidewall to the second sidewall of the memory array;
a second layer in direct contact with the first layer, the second layer comprising silicon, the second layer extending from the third sidewall to the fourth sidewall of the logic circuitry;
an interconnect structure extending through the first layer and the second layer,
wherein the interconnect structure has a first portion that extends through the first layer, and a second portion that extends through the second layer, and
wherein the first portion of the interconnect structure is offset with respect to the second portion of the interconnect structure at an interface between the first and second layers.

17. The integrated circuit memory of claim 16 , wherein each of the first and second layers has a thickness of at least 3000 angstrom.

Assignees

• Intel Corp

Inventors

• Fastow Richard
• Hasnat Khaled
• Majhi Prashant
• Jungroth Owen W
• Parat Krishna

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W72/07354

  changes in dispositions · CPC title