Pixel circuit

Patent metadata

Field	Value
Publication number	US-10923029-B2
Application number	US-201916355846-A
Country	US
Kind code	B2
Filing date	Mar 18, 2019
Priority date	Apr 19, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A pixel circuit including a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor is provided. The third transistor is coupled to the second transistor. The fourth transistor is coupled to the second transistor. The storage capacitor is coupled between the first transistor and the fourth transistor. The fifth transistor is coupled to the fourth transistor. The sixth transistor is coupled to the fourth transistor. The seventh transistor is coupled to the fourth transistor and the light-emitting element. The eighth transistor is coupled to the first transistor.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a light-emitting element, having an anode and a cathode receiving a system low voltage;
a first transistor, having a first terminal receiving a system high voltage, a control terminal receiving a first light-emitting signal, and a second terminal;
a second transistor, having a first terminal receiving the system high voltage, a control terminal receiving the first light-emitting signal and a second terminal;
a third transistor, having a first terminal coupled to the second terminal of the second transistor, a control terminal receiving a first scan signal, and a second terminal receiving a reference voltage;
a fourth transistor, having a first terminal directly connected to the second terminal of the second transistor, a control terminal and a second terminal;
a storage capacitor, directly connected between the second terminal of the first transistor and the control terminal of the fourth transistor;
a fifth transistor, having a first terminal coupled to the control terminal of the fourth transistor, a control terminal receiving the first scan signal and a second terminal coupled to the second terminal of the fourth transistor;
a sixth transistor, having a first terminal coupled to the control terminal of the fourth transistor, a control terminal receiving a second scan signal, and a second terminal receiving a low level voltage or the second scan signal;
a seventh transistor, having a first terminal directly connected to the second terminal of the fourth transistor, a control terminal receiving a second light-emitting signal, and a second terminal directly connected to the anode of the light-emitting element; and
an eighth transistor, having a first terminal receiving a data voltage, a control terminal receiving the first scan signal, and a second terminal coupled to the second terminal of the first transistor,
wherein an enabling period of the first scan signal is longer than an enabling period of the second scan signal, the enabling period of the second scan signal is earlier than the enabling period of the first scan signal, and the enabling period of the second scan signal is partially overlapped with the enabling period of the first scan signal.

2. The pixel circuit as claimed in claim 1 , wherein the first terminal of the sixth transistor is directly coupled to the control terminal of the fourth transistor.

3. The pixel circuit as claimed in claim 1 , wherein the first terminal of the sixth transistor is coupled to the second terminal of the fifth transistor, so as to be coupled to the control terminal of the fourth transistor through the turned-on fifth transistor.

4. The pixel circuit as claimed in claim 3 , further comprising:
a ninth transistor, having a first terminal coupled to the second terminal of the fifth transistor, a control terminal receiving the first scan signal, and a second terminal coupled to the second terminal of the fourth transistor.

5. The pixel circuit as claimed in claim 1 , wherein the second terminal of the sixth transistor is coupled to the second scan signal to receive the low level voltage of the second scan signal.

6. The pixel circuit as claimed in claim 1 , wherein a high level voltage of the second scan signal is greater than the system high voltage.

7. The pixel circuit as claimed in claim 1 , wherein the enabling period of the first scan signal and the enabling period of the second scan signal are completely within a disabling period of the first light-emitting signal.

8. The pixel circuit as claimed in claim 7 , wherein a time length of the disabling period of the first light-emitting signal is substantially equal to a time length of a disabling period of the second light-emitting signal, and the disabling period of the first light-emitting signal is earlier than the disabling period of the second light-emitting signal.

9. The pixel circuit as claimed in claim 1 , wherein the reference voltage is between the system high voltage and the system low voltage.

10. A pixel circuit, comprising:
a light-emitting element, having an anode and a cathode receiving a system low voltage;
a first transistor, having a first terminal receiving a system high voltage, a control terminal receiving a first light-emitting signal, and a second terminal;
a second transistor, having a first terminal receiving the system high voltage, a control terminal receiving the first light-emitting signal and a second terminal;
a third transistor, having a first terminal coupled to the second terminal of the second transistor, a control terminal receiving a first scan signal, and a second terminal receiving a reference voltage;
a fourth transistor, having a first terminal directly connected to the second terminal of the second transistor, a control terminal and a second terminal;
a storage capacitor, directly connected between the second terminal of the first transistor and the control terminal of the fourth transistor;
a fifth transistor, having a first terminal coupled to the control terminal of the fourth transistor, a control terminal receiving the first scan signal and a second terminal coupled to the second terminal of the fourth transistor;
a sixth transistor, having a first terminal coupled to the control terminal of the fourth transistor, a control terminal receiving a second scan signal, and a second terminal receiving a low level voltage or the second scan signal;
a seventh transistor, having a first terminal directly connected to the second terminal of the fourth transistor, a control terminal receiving a second light-emitting signal, and a second terminal directly connected to the anode of the light-emitting element; and
an eighth transistor, having a first terminal receiving a data voltage, a control terminal receiving the first scan signal, and a second terminal coupled to the second terminal of the first transistor,
wherein during an enabling period, the first transistor and the second transistor are turned off, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are turned on, and
wherein an enabling period of the first scan signal is longer than an enabling period of the second scan signal, the enabling period of the second scan signal is earlier than the enabling period of the first scan signal, and the enabling period of the second scan signal is partially overlapped with the enabling period of the first scan signal.

11. The pixel circuit as claimed in claim 10 , wherein the first terminal of the sixth transistor is coupled to the second terminal of the fifth transistor, so as to be coupled to the control terminal of the fourth transistor through the turned-on fifth transistor.

12. The pixel circuit as claimed in claim 11 , further comprising:
a ninth transistor, having a first terminal coupled to the second terminal of the fifth transistor, a control terminal receiving the first scan signal, and a second terminal coupled to the second terminal of the fourth transistor.

13. The pixel circuit as claimed in claim 10 , wherein the second terminal of the sixth transistor is coupled to the second scan signal to receive the low level voltage of the second scan signal.

14. The pixel circuit as claimed in claim 10 , wherein a high level voltage of the second scan signal is greater than the system high voltage.

15. The pixel circuit as claimed in claim 10 , wherein the enabling period of the first scan signal and the enabling period of the second scan signal are completely within a disabling period of the first lig

Assignees

• Au Optronics Corp

Inventors

• Chen Yi-Chiung
• Cheng Mao-Hsun

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2300/0439

  Pixel structures · CPC title