Rapid scan testing of integrated circuit chips

Patent metadata

Field	Value
Publication number	US-10921372-B2
Application number	US-201916511792-A
Country	US
Kind code	B2
Filing date	Jul 15, 2019
Priority date	Jun 1, 2017
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

First claim

What is claimed is:

1. A method comprising:
configuring a first programmable block of a plurality of programmable blocks of an integrated circuit (IC) chip with test logic for carrying out a test on programmable blocks of the plurality of programmable blocks other than the first programmable block;
generating first patterns and first expected results for the test outside the IC chip;
loading the first patterns and the first expected results into memory;
injecting the first patterns from the memory into the other programmable blocks of the IC chip;
obtaining output responses of the other programmable blocks in response to the first patterns, the output responses being obtained by shifting in the injected first patterns through chains of the other programmable blocks and capturing responses of the chains from the shifting;
comparing, by the test logic within the first programmable block, the output responses with the first expected results; and
providing a test result based on the comparison between the output responses and the first expected results.

2. The method of claim 1 and further comprising testing the memory prior to loading the first patterns and the expected results into the memory.

3. The method of claim 1 and further comprising testing the first programmable block prior to loading the first patterns and the expected results into the memory.

4. The method of claim 3 and wherein testing of the first programmable block is carried out with second patterns and second expected results that are not stored in the memory.

5. The method of claim 1 and wherein loading the first patterns and the first expected results into the memory comprises receiving, by the test logic within the first programmable block, the first patterns and the first expected results from input/output pins of the IC chip, and storing, by the test logic within the first programmable block, the first patterns and the first expected results into the memory.

6. The method of claim 1 wherein the test is a scan test, the test logic is scan test logic, and further comprising recording, by the scan test logic within the first programmable block, scan test information for locating failed logic within the IC chip when the scan test result has a failed status.

7. The method of claim 1 and wherein injecting the first patterns from the memory into the other programmable blocks of the IC chip comprises substantially simultaneously injecting, by the test logic within the first programmable block, different patterns from the memory into different chains in the other programmable blocks.

8. The method of claim 7 and wherein comparing, by the test logic within the first programmable block, the output responses with the first expected results comprises substantially simultaneously comparing, by the test logic within the first programmable block, test outputs from the different chains with the first expected results.

9. The method of claim 1 and further comprising reading at least some of the first expected results from the memory when at least some of the first patterns are being loaded into the memory.

10. An apparatus comprising:
a memory; and
a plurality of programmable blocks comprising a first programmable block having scan test logic configured to carry out a scan test on other ones of the plurality of programmable blocks,
the scan test logic is configured to:
receive scan patterns and expected results from interface pins of an IC chip;
load the scan patterns and the expected results into the memory;
inject the scan patterns from the memory into the other ones of the plurality of programmable blocks;
obtain output responses of the other programmable blocks in response to the scan patterns by shifting in the injected scan patterns through scan chains of the other programmable blocks and capture responses of the scan chains from the shifting;
compare the output responses with the expected results; and
provide a scan test result based on the comparison between the output responses and the expected results.

11. The apparatus of claim 10 and wherein the scan test logic is further configured to record scan test information for locating failed logic within the IC chip when the scan test result has a failed status.

12. The apparatus of claim 10 and wherein the scan test logic is further configured to substantially simultaneously inject different ones of the scan patterns from the memory into different scan chains in the other programmable blocks.

13. The apparatus of claim 12 and wherein the scan test logic is further configured to substantially simultaneously compare scan test outputs from the different scan chains with the expected results.

14. The apparatus of claim 10 and wherein the scan test logic is configured to read at least some of the expected results from the memory when at least some of the scan patterns are being loaded into the memory.

15. A tester coupleable to an integrated circuit (IC) chip under test, the tester comprising:
tester inputs and tester outputs for the IC chip under test having a plurality of input/output (I/O) pins, the plurality of I/O pins including high speed and low speed I/O pins, the tester inputs communicatively coupled to the high speed I/O pins and not coupled to any of the low speed I/O pins; and
a driver to pump scan patterns and expected results from the tester inputs to the high speed I/O pins to enable the IC chip to carry out scan test operations internal to the IC chip using the scan patterns and the expected results to determine a scan test result.

16. The tester of claim 15 and wherein the circuit further comprises a plurality of programmable blocks comprising a first programmable block having scan test logic configured to carry out the scan test operations internal to the circuit on other ones of the plurality of programmable blocks, and configured to determine the scan test result.

17. The tester of claim 16 and further comprising a memory, and wherein the scan test logic is configured to:
receive the scan patterns and the expected results from the I/O pins of the circuit;
load the scan patterns and the expected results into the memory;
inject the scan patterns from the memory into the other ones of the plurality of programmable blocks;
obtain an output responses of the other programmable blocks in response to the scan patterns by shifting in the injected scan patterns through scan chains of the other programmable blocks and capture responses of the scan chains from the shifting;
compare the output responses with the expected results; and
provide the scan test result based on the comparison between the output responses and the expected results.

18. The tester of claim 17 and wherein the scan test logic is further configured to record scan test information for locating failed logic within the circuit when the scan test result has a failed status.

19. The tester of claim 17 and wherein the scan test logic is further configured to substantially simultaneously inject different ones of the scan patterns from the memory into different scan chains in the other programmable blocks.

20. The tester of claim 19 and wherein the scan test logic is further configured to substantially simultaneously compare scan test outputs from the different scan chains with the expected results.

Assignees

• Seagate Technology Llc

Inventors

• Bhagwat Rajesh Maruti
• Kabra Nitin Satishchandra
• Shah Jay

Classifications

• G01R31/318563 Primary

  Multiple simultaneous testing of subparts · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G01R31/318566

  Comparators; Diagnosing the device under test · CPC title

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title