Programmable scan shift testing

Patent metadata

Field	Value
Publication number	US-10921371-B2
Application number	US-201715641690-A
Country	US
Kind code	B2
Filing date	Jul 5, 2017
Priority date	Jul 5, 2017
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

The disclosed technology facilitates programmable scan shift testing for a scan chain including at least a first segment of scan-flops connected in series with a second segment of scan-flops. The scan chain includes at least a first multiplexor positioned between the first segment and the second segment that is configured to selectively supply scan input from a test controller to the second segment while preventing the second segment from receiving an output of the first segment.

First claim

What is claimed is:

1. A integrated circuit (IC) comprising:
multiple scan chains each including a series of scan-flops;
a plurality of leading gates each functioning as an on/off trigger for a corresponding one of the multiple scan chains, each of the plurality of leading gates having a first gate input configured to receive a test pattern programmed via a first scan-in port and a second gate input configured to receive an on/off scan chain indicator programmed via a second scan-in port;
a group of scan-flops external to the multiple scan chains, each scan-flop in the group being directly connected to an associated gate of the plurality of leading gates and storing the on/off scan chain indictor for the associated gate, the on/off scan chain indicator functioning to configure a corresponding one of the multiple scan chains in an on or off state.

2. The IC of claim 1 , wherein the series of scan-flops in a first chain of the multiple scan chains includes at least a first segment of scan-flops and a second segment of scan-flops, the second segment configured to receive an output from the first segment, and wherein the IC further includes:
a first multiplexor positioned between the first segment and the second segment that is configured to selectively supply scan input from a test controller to the second segment while preventing the second segment from receiving an output of the first segment; and
one or more logic gates configured to reset the scan-flops of the first segment while the first multiplexor supplies the scan input to the second segment.

3. The IC of claim 2 , wherein the one or more logic gates include an OR gate receiving as an input a selection line input of the first multiplexor and an input from a reset pin, the OR gate supplying an output to the first segment that selectively configures the scan-flops of the first segment in a reset mode.

4. The IC of claim 2 , further comprising one or more logic gates configured to mask a clock input to the first segment while the first multiplexor is supplying the scan input to the second segment.

5. The IC of claim 2 , wherein the first chain further includes a third segment separated from the second segment by a second multiplexor, the second multiplexor positioned between the first segment and the second segment and configured to selectively supply the scan input to the third segment while preventing the third segment from receiving output of the first segment and output of the second segment.

6. The IC of claim 1 , wherein the plurality of leading gates consists of a plurality of AND gates.

7. Apparatus comprising:
multiple scan chains connected in series;
a plurality of leading gates, each leading gate of the plurality of leading gates being coupled to one of the multiple scan chains and including:
a first gate input configured to receive a scan test pattern;
a second gate input configured to receive an on/off scan chain indicator; and
a gate output that functions as an on/off trigger for the associated scan chain;

a test controller including computer-executable instructions stored in memory and executable by a processor to:
load the test pattern into the first gate input of the leading gate connected to a first scan chain of the multiple scan chains; and
selectively mask a second scan chain of the multiple scan chains by loading the on/off scan chain indictor to a scan-flop directly connected to the second gate input of the leading gate of the second scan chain, the selective masking preventing the second scan chain from receiving the scan test pattern from the first scan chain.

8. The apparatus of claim 7 , further comprising:
supplying a selected decoder input to a selection line of a first multiplexor positioned between a first segment and a second segment of the first scan chain, the decoder input controlling the first multiplexor to supply values of the selected scan test pattern to the second segment while preventing the second segment from receiving an output of the first segment.

9. The apparatus of claim 8 , wherein the first scan chain is coupled to one or more logic gates configured to reset scan-flops of the first segment while the test controller supplies the selected decoder input to the selection line of the first multiplexor.

10. The apparatus of claim 9 , wherein the one or more logic gates include an OR gate configured to receive the selected decoder input and an input from a reset pin, the OR gate supplying an output to the first segment of the first scan chain to configure the first segment in a reset mode responsive to receipt of the selected decoder input along the selection line of the first multiplexor.

11. The apparatus of claim 9 , wherein the first scan chain is further coupled to one or more logic gates configured to mask a clock input to the first segment of the first scan chain responsive to receipt of the selected decoder input along the selection line of the first multiplexor.

12. A method comprising:
loading a scan test pattern into a first scan chain during a loading sequence of a scan chain test, the first scan chain being included in a series of multiple scan chains each being coupled to a corresponding leading gate of a plurality of leading gates, each of the leading gates including:
a first gate input configured to receive a scan test pattern;
a second gate input configured to receive an on/off scan chain indicator; and
a gate output that functions as an on/off trigger for the associated scan chain;
and
selectively masking inputs to a select scan chain of the multiple scan chains by loading the on/off scan chain indicator to a scan-flop directly connected to the second gate input of the leading gate of the select scan chain, the selective masking preventing the select scan chain from receiving the scan test pattern from the first scan chain.

13. The method of claim 12 , further comprising:
supplying a selected decoder input to a selection line of a first multiplexor positioned between a first segment and a second segment of the first scan chain, the decoder input controlling the first multiplexor to supply values of the selected scan test pattern to the second segment while preventing the second segment from receiving an output of the first segment;
loading the values of the selected scan test pattern to a primary scan input coupled to the first multiplexor;
providing a clock pulse input to scan-flops of the second segment; and
unloading values stored in the second segment subsequent to the receipt of the clock pulse.

14. The method of claim 13 , further comprising:
supplying the selected decoder input to one or more logic gates configured to reset scan-flops of the first segment while the selected decoder input controls the first multiplexor to prevent outputs of the first segment of the scan chain from being received by the second segment of the chain.

15. The method of claim 13 , further comprising:
supplying the selected decoder input to an OR gate configured to also receive an input from a reset pin, the OR gate supplying an output to the first segment of the first scan chain to configure the first segment in a reset mode when the selected decoder input is supplied the selection line of the first multiplexor.

16. The method of claim 13 , further comprising:
supplying the selected decoder input to one or more logic gates configured to mask a clock input to the first segment of the first scan chain responsive to receipt of the selected decoder input along the selection line of the first multiplexor.

Assignees

• Seagate Technology Llc

Inventors

• Shah Jay
• Bhasale Aniruddha Mukund

Classifications

• G01R31/318544 Primary

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/318555

  Control logic · CPC title

• G01R31/318558

  Addressing or selecting of subparts of the device under test · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title